mirror of https://github.com/m-labs/artiq.git
test: rewrite tests using ttl_inout to use loop_{in,out} (#265).
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@ -6,18 +6,17 @@ from artiq.test.hardware_testbench import ExperimentCase
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class CreateTTLPulse(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("ttl_inout")
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self.setattr_device("loop_in")
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self.setattr_device("loop_out")
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@kernel
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def run(self):
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self.ttl_inout.output()
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delay_mu(100)
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with parallel:
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self.ttl_inout.gate_both_mu(1200)
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self.loop_in.gate_both_mu(1200)
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with sequential:
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delay_mu(100)
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self.ttl_inout.pulse_mu(1000)
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self.ttl_inout.count()
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self.loop_out.pulse_mu(1000)
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self.loop_in.count()
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class AnalyzerTest(ExperimentCase):
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@ -20,7 +20,7 @@ class RTT(EnvExperiment):
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def run(self):
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self.ttl_inout.output()
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delay(1*us)
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with parallel:
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with interleave:
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# make sure not to send two commands into the same RTIO
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# channel with the same timestamp
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self.ttl_inout.gate_rising(5*us)
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@ -101,28 +101,6 @@ class Watchdog(EnvExperiment):
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pass
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class LoopbackCount(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("ttl_inout")
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self.setattr_argument("npulses")
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def set_count(self, count):
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self.set_dataset("count", count)
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@kernel
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def run(self):
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self.ttl_inout.output()
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delay(5*us)
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with parallel:
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self.ttl_inout.gate_rising(10*us)
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with sequential:
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for i in range(self.npulses):
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delay(25*ns)
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self.ttl_inout.pulse(25*ns)
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self.set_dataset("count", self.ttl_inout.count())
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class Underflow(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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@ -185,17 +163,6 @@ class Handover(EnvExperiment):
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class CoredeviceTest(ExperimentCase):
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@unittest.skipUnless(artiq_low_latency,
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"timings are dependent on CPU load and network conditions")
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def test_rtt(self):
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self.execute(RTT)
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rtt = self.dataset_mgr.get("rtt")
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print(rtt)
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self.assertGreater(rtt, 0*ns)
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self.assertLess(rtt, 100*ns)
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@unittest.skipUnless(artiq_low_latency,
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"timings are dependent on CPU load and network conditions")
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def test_loopback(self):
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self.execute(Loopback)
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rtt = self.dataset_mgr.get("rtt")
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@ -208,8 +175,6 @@ class CoredeviceTest(ExperimentCase):
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count = self.dataset_mgr.get("count")
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self.assertEqual(count, 10)
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@unittest.skipUnless(artiq_low_latency,
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"timings are dependent on CPU load and network conditions")
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def test_pulse_rate(self):
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self.execute(PulseRate)
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rate = self.dataset_mgr.get("pulse_rate")
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@ -217,12 +182,6 @@ class CoredeviceTest(ExperimentCase):
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self.assertGreater(rate, 100*ns)
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self.assertLess(rate, 2500*ns)
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def test_loopback_count(self):
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npulses = 2
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self.execute(LoopbackCount, npulses=npulses)
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count = self.dataset_mgr.get("count")
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self.assertEqual(count, npulses)
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def test_underflow(self):
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with self.assertRaises(RTIOUnderflow):
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self.execute(Underflow)
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@ -157,7 +157,6 @@
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"command": "lda_controller -p {port} --bind {bind} --simulation"
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},
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"ttl_inout": "pmt0",
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"ttl_out": "ttl0",
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"ttl_out_serdes": "ttl0",
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