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serwb/phy/master: fix slave ready detection by filtering possible glitches on rx data (seems to happen when RTM fpga is not loaded)

This commit is contained in:
Florent Kermarrec 2018-04-30 23:59:56 +02:00
parent 5a683ddd1f
commit 64c8eee28d
1 changed files with 4 additions and 1 deletions
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5
artiq/gateware/serwb/phy.py
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@ -58,7 +58,10 @@ class _SerdesMasterInit(Module):
) )
fsm.act("SEND_PATTERN", fsm.act("SEND_PATTERN",
If(~serdes.rx_idle, If(~serdes.rx_idle,
NextState("WAIT_STABLE") timer.wait.eq(1),
If(timer.done,
NextState("CHECK_PATTERN")
)
), ),
serdes.tx_comma.eq(1) serdes.tx_comma.eq(1)
) )