mirror of https://github.com/m-labs/artiq.git
kasli: fix DRTIO satellite QPLL refclksel
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@ -330,7 +330,7 @@ class Satellite(BaseSoC):
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i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
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o_O=si5324_clkout_buf)
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qpll_drtio_settings = QPLLSettings(
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refclksel=0b010,
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refclksel=0b001,
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fbdiv=4,
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fbdiv_45=5,
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refclk_div=1)
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