From 642a305c6a9c5e6f9bcd5ff631ab79d092660adf Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 30 Dec 2019 20:01:06 +0800 Subject: [PATCH] wrpll: remove unnecessary delay Counting now happens in the sys domain with no CDC between counter and CPU. --- artiq/firmware/libboard_artiq/wrpll.rs | 1 - 1 file changed, 1 deletion(-) diff --git a/artiq/firmware/libboard_artiq/wrpll.rs b/artiq/firmware/libboard_artiq/wrpll.rs index 8c35c0cb8..29910723d 100644 --- a/artiq/firmware/libboard_artiq/wrpll.rs +++ b/artiq/firmware/libboard_artiq/wrpll.rs @@ -269,7 +269,6 @@ fn get_frequencies() -> (u32, u32, u32) { csr::wrpll::frequency_counter_update_en_write(1); clock::spin_us(200_000); // wait for at least one update csr::wrpll::frequency_counter_update_en_write(0); - clock::spin_us(1); let helper = csr::wrpll::frequency_counter_counter_helper_read(); let main = csr::wrpll::frequency_counter_counter_rtio_read(); let cdr = csr::wrpll::frequency_counter_counter_rtio_rx0_read();