diff --git a/artiq/gateware/dsp/fir.py b/artiq/gateware/dsp/fir.py
index 6f1535528..cc0635106 100644
--- a/artiq/gateware/dsp/fir.py
+++ b/artiq/gateware/dsp/fir.py
@@ -65,6 +65,7 @@ class FIR(Module):
             if c == 0 or c in coefficients[i + 1:]:
                 continue
             m = Signal((width + shift, True))
+            m.attr.add("use_multiplier")
             self.sync += m.eq(c*reduce(add, [
                 xj for xj, cj in zip(x[::-1], coefficients) if cj == c
             ]))
@@ -108,6 +109,7 @@ class ParallelFIR(Module):
                 if c == 0 or c in coefficients[i + 1:]:
                     continue
                 m = Signal((width + shift, True))
+                m.attr.add("use_multiplier")
                 self.sync += m.eq(c*reduce(add, [
                     xj for xj, cj in zip(x[-1 - j::-1], coefficients) if cj == c
                 ]))
diff --git a/artiq/gateware/targets/phaser.py b/artiq/gateware/targets/phaser.py
index 9cc7c1559..6f68517a7 100755
--- a/artiq/gateware/targets/phaser.py
+++ b/artiq/gateware/targets/phaser.py
@@ -169,6 +169,9 @@ class Phaser(MiniSoC, AMPSoC):
                          ident=artiq_version,
                          **kwargs)
         AMPSoC.__init__(self)
+        self.platform.toolchain.attr_translate["use_multiplier"] = \
+            ("use_dsp48", "yes")
+
         self.platform.toolchain.bitstream_commands.extend([
             "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
         ])