From 64182059062bfc5cd04d004c88eca25b315916eb Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Wed, 28 Jun 2017 19:09:21 +0200 Subject: [PATCH] dsp.fir: use pipelin-reset --- artiq/gateware/dsp/fir.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/dsp/fir.py b/artiq/gateware/dsp/fir.py index 4fa2e9c5f..0a63ac133 100644 --- a/artiq/gateware/dsp/fir.py +++ b/artiq/gateware/dsp/fir.py @@ -83,7 +83,7 @@ class ParallelFIR(Module): ### # Delay line: increasing delay - x = [Signal((w.A, True)) for _ in range(n + p - 1)] + x = [Signal((w.A, True), reset_less=True) for _ in range(n + p - 1)] x_shift = w.A - width # reduce by pre-adder gain x_shift -= bits_for(max(cs.count(c) for c in cs if c) - 1) @@ -98,7 +98,7 @@ class ParallelFIR(Module): self.sync += xi.eq(xj) for delay in range(p): - o = Signal((w.P, True)) + o = Signal((w.P, True), reset_less=True) self.comb += self.o[delay].eq(o >> c_shift + x_shift) # Make products for i, c in enumerate(cs):