From 63f7899f93e7de6720d3b9b9bbe5c85d4676ecc2 Mon Sep 17 00:00:00 2001 From: whitequark Date: Sun, 10 Jan 2016 20:25:58 +0000 Subject: [PATCH] Commit missing parts of 7f914a0. --- artiq/compiler/transforms/llvm_ir_generator.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/artiq/compiler/transforms/llvm_ir_generator.py b/artiq/compiler/transforms/llvm_ir_generator.py index c86118c45..23ead974e 100644 --- a/artiq/compiler/transforms/llvm_ir_generator.py +++ b/artiq/compiler/transforms/llvm_ir_generator.py @@ -191,6 +191,7 @@ class LLVMIRGenerator: and len(lltyp.elements) <= 2: return not any([self.needs_sret(elt, may_be_large=False) for elt in lltyp.elements]) else: + assert isinstance(lltyp, ll.Type) return True def has_sret(self, functy): @@ -1239,7 +1240,7 @@ class LLVMIRGenerator: return self.llbuilder.ret_void() else: llvalue = self.map(insn.value()) - if self.needs_sret(llvalue): + if self.needs_sret(llvalue.type): self.llbuilder.store(llvalue, self.llfunction.args[0]) return self.llbuilder.ret_void() else: