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drtio: partially fix tests

This commit is contained in:
Sebastien Bourdeauducq 2023-01-06 18:33:13 +08:00
parent 7dafdfe2f7
commit 63f1a6d197
1 changed files with 3 additions and 3 deletions
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6
artiq/gateware/test/drtio/test_full_stack.py
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@ -52,7 +52,7 @@ class DUT(Module):
self.ttl1 = Signal() self.ttl1 = Signal()
self.transceivers = DummyTransceiverPair(nwords) self.transceivers = DummyTransceiverPair(nwords)
self.submodules.tsc_master = rtio.TSC("async") self.submodules.tsc_master = rtio.TSC()
self.submodules.master = DRTIOMaster(self.tsc_master, self.submodules.master = DRTIOMaster(self.tsc_master,
self.transceivers.alice) self.transceivers.alice)
self.submodules.master_ki = rtio.KernelInitiator(self.tsc_master, self.submodules.master_ki = rtio.KernelInitiator(self.tsc_master,
@ -144,8 +144,8 @@ class OutputsTestbench:
class TestFullStack(unittest.TestCase): class TestFullStack(unittest.TestCase):
clocks = {"sys": 8, "rtio_rx": 5, clocks = {"sys": 8, "rtio_rx": 8,
"rio": 5, "rio_phy": 5} "rio": 8, "rio_phy": 8}
def test_pulses(self): def test_pulses(self):
tb = OutputsTestbench() tb = OutputsTestbench()