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compiler: enabled vectorize option

This commit is contained in:
pca006132 2021-01-11 15:11:50 +08:00
parent 6a5f5088e2
commit 636898c302
2 changed files with 5 additions and 0 deletions
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1
RELEASE_NOTES.rst
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@ -28,6 +28,7 @@ Highlights:
- SERDES TTL inputs can now detect edges on pulses that are shorter - SERDES TTL inputs can now detect edges on pulses that are shorter
than the RTIO period (https://github.com/m-labs/artiq/issues/1432) than the RTIO period (https://github.com/m-labs/artiq/issues/1432)
- Improved performance for kernel RPC involving list and array. - Improved performance for kernel RPC involving list and array.
- Improved performance for computation involving loops.
* Coredevice SI to mu conversions now always return valid codes, or raise a ``ValueError``. * Coredevice SI to mu conversions now always return valid codes, or raise a ``ValueError``.
* Zotino now exposes ``voltage_to_mu()`` * Zotino now exposes ``voltage_to_mu()``
* ``ad9910``: The maximum amplitude scale factor is now ``0x3fff`` (was ``0x3ffe`` * ``ad9910``: The maximum amplitude scale factor is now ``0x3fff`` (was ``0x3ffe``

4
artiq/compiler/targets.py
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@ -105,7 +105,11 @@ class Target:
return llmachine return llmachine
def optimize(self, llmodule): def optimize(self, llmodule):
pmb = llvm.create_pass_manager_builder()
pmb.slp_vectorize = True
pmb.loop_vectorize = True
llpassmgr = llvm.create_module_pass_manager() llpassmgr = llvm.create_module_pass_manager()
pmb.populate(llpassmgr)
# Register our alias analysis passes. # Register our alias analysis passes.
llpassmgr.add_basic_alias_analysis_pass() llpassmgr.add_basic_alias_analysis_pass()