mirror of https://github.com/m-labs/artiq.git
sayma_amc: use high-resolution TTL on SMAs (#792)
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@ -18,7 +18,7 @@ from artiq.gateware import fmcdio_vhdci_eem
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from artiq.gateware import serwb, remote_csr
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from artiq.gateware import rtio
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from artiq.gateware import jesd204_tools
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from artiq.gateware.rtio.phy import ttl_simple, sawg
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_ultrascale, sawg
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from artiq.gateware.drtio.transceiver import gth_ultrascale
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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@ -163,6 +163,9 @@ class Standalone(MiniSoC, AMPSoC, RTMCommon):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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# To work around Ultrascale issues (https://www.xilinx.com/support/answers/67885.html),
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# we generate the multiplied RTIO clock using the DRTIO GTH transceiver.
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# Since there is no DRTIO here and therefoere no multiplied clock, we use ttl_simple.
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sma_io = platform.request("sma_io", 0)
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self.comb += sma_io.direction.eq(1)
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phy = ttl_simple.Output(sma_io.level)
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@ -338,12 +341,12 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 0)
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self.comb += sma_io.direction.eq(1)
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phy = ttl_simple.Output(sma_io.level)
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phy = ttl_serdes_ultrascale.Output(4, sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 1)
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self.comb += sma_io.direction.eq(0)
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phy = ttl_simple.InOut(sma_io.level)
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phy = ttl_serdes_ultrascale.InOut(4, sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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@ -497,12 +500,12 @@ class Master(MiniSoC, AMPSoC):
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 0)
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self.comb += sma_io.direction.eq(1)
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phy = ttl_simple.Output(sma_io.level)
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phy = ttl_serdes_ultrascale.Output(4, sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 1)
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self.comb += sma_io.direction.eq(0)
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phy = ttl_simple.InOut(sma_io.level)
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phy = ttl_serdes_ultrascale.InOut(4, sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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@ -575,12 +578,12 @@ class Satellite(BaseSoC, RTMCommon):
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 0)
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self.comb += sma_io.direction.eq(1)
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phy = ttl_simple.Output(sma_io.level)
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phy = ttl_serdes_ultrascale.Output(4, sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 1)
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self.comb += sma_io.direction.eq(0)
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phy = ttl_simple.InOut(sma_io.level)
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phy = ttl_serdes_ultrascale.InOut(4, sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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