From 62320432a559652bb436e522a9112fe29f653f47 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Wed, 1 Nov 2017 14:45:07 +0100 Subject: [PATCH] artiq_flash: fix sayma amc tap/pld index --- artiq/frontend/artiq_flash.py | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/artiq/frontend/artiq_flash.py b/artiq/frontend/artiq_flash.py index e675b68fa..4924a8107 100755 --- a/artiq/frontend/artiq_flash.py +++ b/artiq/frontend/artiq_flash.py @@ -109,11 +109,11 @@ class ProgrammerJtagSpi7(Programmer): preinit_commands) self.init() - def load(self, bitfile): - self.prog.append("pld load 0 " + bitfile) + def load(self, bitfile, pld=0): + self.prog.append("pld load {} {{{}}}".format(pld, bitfile)) - def proxy(self, proxy_bitfile): - self.prog.append("jtagspi_init 0 {{{}}}".format(proxy_bitfile)) + def proxy(self, proxy_bitfile, pld=0): + self.prog.append("jtagspi_init {} {{{}}}".format(pld, proxy_bitfile)) def flash_binary(self, flashno, address, filename): # jtagspi_program supports only one flash @@ -143,9 +143,9 @@ class ProgrammerSayma(Programmer): "adapter_khz 5000", "transport select jtag", - "source [find cpld/xilinx-xc7.cfg]", + "source [find cpld/xilinx-xc7.cfg]", # tap 0, pld 0 "set CHIP XCKU040", - "source [find cpld/xilinx-xcu.cfg]", + "source [find cpld/xilinx-xcu.cfg]", # tap 1, pld 1 "set XILINX_USER1 0x02", "set XILINX_USER2 0x03", @@ -156,14 +156,12 @@ class ProgrammerSayma(Programmer): ] self.init() - def load(self, bitfile): - self.prog.append("pld load 0 " + bitfile) + def load(self, bitfile, pld=1): + self.prog.append("pld load {} {{{}}}".format(pld, bitfile)) - def proxy(self, proxy_bitfile): - self.prog += [ - "pld load 0 " + proxy_bitfile, - "reset halt" - ] + def proxy(self, proxy_bitfile, pld=1): + self.load(proxy_bitfile, pld) + self.prog.append("reset halt") def flash_binary(self, flashno, address, filename): self.prog += [