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artiq_flash: fix sayma amc tap/pld index

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This commit is contained in:
Robert Jördens 2017-11-01 14:45:07 +01:00
parent e16ab69f01
commit 62320432a5
1 changed files with 11 additions and 13 deletions
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24
artiq/frontend/artiq_flash.py
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@ -109,11 +109,11 @@ class ProgrammerJtagSpi7(Programmer):
preinit_commands)
self.init()
def load(self, bitfile):
self.prog.append("pld load 0 " + bitfile)
def load(self, bitfile, pld=0):
self.prog.append("pld load {} {{{}}}".format(pld, bitfile))
def proxy(self, proxy_bitfile):
self.prog.append("jtagspi_init 0 {{{}}}".format(proxy_bitfile))
def proxy(self, proxy_bitfile, pld=0):
self.prog.append("jtagspi_init {} {{{}}}".format(pld, proxy_bitfile))
def flash_binary(self, flashno, address, filename):
# jtagspi_program supports only one flash
@ -143,9 +143,9 @@ class ProgrammerSayma(Programmer):
"adapter_khz 5000",
"transport select jtag",
"source [find cpld/xilinx-xc7.cfg]",
"source [find cpld/xilinx-xc7.cfg]", # tap 0, pld 0
"set CHIP XCKU040",
"source [find cpld/xilinx-xcu.cfg]",
"source [find cpld/xilinx-xcu.cfg]", # tap 1, pld 1
"set XILINX_USER1 0x02",
"set XILINX_USER2 0x03",
@ -156,14 +156,12 @@ class ProgrammerSayma(Programmer):
]
self.init()
def load(self, bitfile):
self.prog.append("pld load 0 " + bitfile)
def load(self, bitfile, pld=1):
self.prog.append("pld load {} {{{}}}".format(pld, bitfile))
def proxy(self, proxy_bitfile):
self.prog += [
"pld load 0 " + proxy_bitfile,
"reset halt"
]
def proxy(self, proxy_bitfile, pld=1):
self.load(proxy_bitfile, pld)
self.prog.append("reset halt")
def flash_binary(self, flashno, address, filename):
self.prog += [