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https://github.com/m-labs/artiq.git
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moninj: dds inj: extract shared code
detect urukul already init in more than one way detect ad9912 channel already init
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@ -9,7 +9,7 @@ from sipyco.sync_struct import Subscriber
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from artiq.coredevice.comm_moninj import *
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from artiq.coredevice.ad9910 import _AD9910_REG_PROFILE0, _AD9910_REG_PROFILE7, _AD9910_REG_FTW
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from artiq.coredevice.ad9912_reg import AD9912_POW1
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from artiq.coredevice.ad9912_reg import AD9912_POW1, AD9912_SER_CONF
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from artiq.gui.tools import LayoutWidget
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from artiq.gui.flowlayout import FlowLayout
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@ -549,33 +549,56 @@ class _DeviceManager:
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scheduling["flush"])
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logger.info("Submitted '%s', RID is %d", title, rid)
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def dds_set_frequency(self, dds_channel, dds_model, freq):
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def _dds_faux_injection(self, dds_channel, dds_model, action, title, log_msg):
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# create kernel and fill it in and send-by-content
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# initialize CPLD (if applicable)
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if dds_model.is_urukul:
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# TODO: reimplement cache (simple "was init")
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#
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# urukuls need CPLD init and switch to on
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# keep previous config if it was set already
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cpld_dev = """self.setattr_device("core_cache")
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self.setattr_device("{}")""".format(dds_model.cpld)
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cpld_init = """cfg = self.core_cache.get("_{cpld}_cfg")
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if len(cfg) > 0:
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self.{cpld}.cfg_reg = cfg[0]
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else:
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# `sta`/`rf_sw`` variables are guaranteed for urukuls
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# so {action} can use it
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# if there's no RF enabled, CPLD may have not been initialized
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#
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# but if there is, it has
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cpld_init = """delay(15*ms)
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was_init = self.core_cache.get("_{cpld}_init")
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sta = self.{cpld}.sta_read()
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rf_sw = urukul_sta_rf_sw(sta)
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if rf_sw == 0 and len(was_init) == 0:
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delay(15*ms)
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self.{cpld}.init()
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self.core_cache.put("_{cpld}_cfg", [self.{cpld}.cfg_reg])
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cfg = self.core_cache.get("_{cpld}_cfg")
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self.core_cache.put("_{cpld}_init", [1])
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""".format(cpld=dds_model.cpld)
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cfg_sw = """self.{}.cfg_sw(True)
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cfg[0] = self.{}.cfg_reg
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""".format(dds_channel, dds_model.cpld)
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else:
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cpld_dev = ""
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cpld_init = ""
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cfg_sw = ""
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# AD9912/9910: init channel (if uninitialized)
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if dds_model.dds_type == "AD9912":
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# 0xFF before init, 0x99 after
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channel_init = """
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delay(10*ms)
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if self.{dds_channel}.read({cfgreg}, length=1) == 0xFF:
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delay(10*ms)
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self.{dds_channel}.init()
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""".format(dds_channel=dds_channel, cfgreg=AD9912_SER_CONF)
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elif dds_model.dds_type == "AD9910":
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# TODO: verify AD9910 behavior (when we have hardware)
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channel_init = "self.{dds_channel}.init()".format(dds_channel)
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else:
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channel_init = "self.{dds_channel}.init()".format(dds_channel)
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dds_exp = textwrap.dedent("""
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from artiq.experiment import *
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from artiq.coredevice.urukul import *
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class SetDDS(EnvExperiment):
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class {title}(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("{dds_channel}")
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@ -585,53 +608,57 @@ class _DeviceManager:
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def run(self):
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self.core.break_realtime()
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{cpld_init}
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delay(5*ms)
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self.{dds_channel}.init()
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self.{dds_channel}.set({freq})
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{cfg_sw}
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""".format(dds_channel=dds_channel, freq=freq,
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{channel_init}
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delay(15*ms)
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{action}
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""".format(title=title, action=action,
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dds_channel=dds_channel,
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cpld_dev=cpld_dev, cpld_init=cpld_init,
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cfg_sw=cfg_sw))
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channel_init=channel_init))
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asyncio.ensure_future(
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self._submit_by_content(
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dds_exp,
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"SetDDS",
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"Set DDS {} {}MHz".format(dds_channel, freq/1e6)))
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title,
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log_msg))
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def dds_set_frequency(self, dds_channel, dds_model, freq):
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if dds_model.is_urukul:
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ch_no = "ch_no = self.{ch}.chip_select - 4"
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else:
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ch_no = "ch_no = self.{ch}.channel"
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action = """
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{ch_no}
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self.{ch}.set({freq})
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self.{cpld}.cfg_switches(rf_sw | 1 << ch_no)
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""".format(freq=freq, cpld=dds_model.cpld,
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ch=dds_channel, ch_no=ch_no.format(ch=dds_channel))
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self._dds_faux_injection(
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dds_channel,
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dds_model,
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action,
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"SetDDS",
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"Set DDS {} {}MHz".format(dds_channel, freq/1e6))
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def dds_channel_toggle(self, dds_channel, dds_model, sw=True):
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# urukul only
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toggle_exp = textwrap.dedent("""
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from artiq.experiment import *
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class ToggleDDS(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("{ch}")
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self.setattr_device("core_cache")
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self.setattr_device("{cpld}")
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@kernel
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def run(self):
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self.core.break_realtime()
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cfg = self.core_cache.get("_{cpld}_cfg")
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if len(cfg) > 0:
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self.{cpld}.cfg_reg = cfg[0]
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else:
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delay(15*ms)
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self.{cpld}.init()
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self.core_cache.put("_{cpld}_cfg", [self.{cpld}.cfg_reg])
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cfg = self.core_cache.get("_{cpld}_cfg")
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delay(5*ms)
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self.{ch}.init()
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self.{ch}.cfg_sw({sw})
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cfg[0] = self.{cpld}.cfg_reg
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""".format(ch=dds_channel, cpld=dds_model.cpld, sw=sw))
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asyncio.ensure_future(
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self._submit_by_content(
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toggle_exp,
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"ToggleDDS",
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"Toggle DDS {} {}".format(dds_channel, "on" if sw else "off"))
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if sw:
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switch = "| 1 << ch_no"
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else:
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switch = "& ~(1 << ch_no)"
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action = """
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ch_no = self.{dds_channel}.chip_select - 4
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self.{cpld}.cfg_switches(rf_sw {switch})
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""".format(
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dds_channel=dds_channel,
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cpld=dds_model.cpld,
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switch=switch
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)
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self._dds_faux_injection(
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dds_channel,
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dds_model,
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action,
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"ToggleDDS",
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"Toggle DDS {} {}".format(dds_channel, "on" if sw else "off"))
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def setup_ttl_monitoring(self, enable, channel):
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if self.mi_connection is not None:
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