M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-26 11:48:27 +08:00
Code Issues Projects Releases Wiki Activity

serwb: fix rx_comma detection

Browse Source
This commit is contained in:
Florent Kermarrec 2018-05-07 23:54:35 +02:00
parent bfa7637760
commit 60fd362d57
2 changed files with 12 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
artiq/gateware/serwb/kusphy.py
View File

@ -205,7 +205,11 @@ class KUSSerdes(Module):
decoders[3].input.eq(rx_bitslip.o[30:40]), decoders[3].input.eq(rx_bitslip.o[30:40]),
self.rx_k.eq(Cat(*[decoders[i].k for i in range(4)])), self.rx_k.eq(Cat(*[decoders[i].k for i in range(4)])),
self.rx_d.eq(Cat(*[decoders[i].d for i in range(4)])), self.rx_d.eq(Cat(*[decoders[i].d for i in range(4)])),
self.rx_comma.eq((decoders[0].k == 1) & (decoders[0].d == K(28,5))) self.rx_comma.eq(
(decoders[0].k == 1) & (decoders[0].d == K(28,5)) &
(decoders[1].k == 0) & (decoders[1].d == 0) &
(decoders[2].k == 0) & (decoders[2].d == 0) &
(decoders[3].k == 0) & (decoders[3].d == 0))
] ]
idle_timer = WaitTimer(32) idle_timer = WaitTimer(32)

6
artiq/gateware/serwb/s7phy.py
View File

@ -216,7 +216,11 @@ class S7Serdes(Module):
decoders[3].input.eq(rx_bitslip.o[30:40]), decoders[3].input.eq(rx_bitslip.o[30:40]),
self.rx_k.eq(Cat(*[decoders[i].k for i in range(4)])), self.rx_k.eq(Cat(*[decoders[i].k for i in range(4)])),
self.rx_d.eq(Cat(*[decoders[i].d for i in range(4)])), self.rx_d.eq(Cat(*[decoders[i].d for i in range(4)])),
self.rx_comma.eq((decoders[0].k == 1) & (decoders[0].d == K(28,5))) self.rx_comma.eq(
(decoders[0].k == 1) & (decoders[0].d == K(28,5)) &
(decoders[1].k == 0) & (decoders[1].d == 0) &
(decoders[2].k == 0) & (decoders[2].d == 0) &
(decoders[3].k == 0) & (decoders[3].d == 0))
] ]
idle_timer = WaitTimer(32) idle_timer = WaitTimer(32)