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kasli: ignore OSERDESE2->ISERDESE2 timing path on DRTIO targets as well

This commit is contained in:
Sebastien Bourdeauducq 2018-03-29 10:12:02 +08:00
parent 416232cb64
commit 605292535c
1 changed files with 14 additions and 9 deletions
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23
artiq/gateware/targets/kasli.py
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@ -80,6 +80,17 @@ class _RTIOCRG(Module, AutoCSR):
] ]
def fix_serdes_timing_path(platform):
# ignore timing of path from OSERDESE2 through the pad to ISERDESE2
platform.add_platform_command(
"set_false_path -quiet "
"-through [get_pins -filter {{REF_PIN_NAME == OQ || REF_PIN_NAME == TQ}} "
"-of [get_cells -filter {{REF_NAME == OSERDESE2}}]] "
"-to [get_pins -filter {{REF_PIN_NAME == D}} "
"-of [get_cells -filter {{REF_NAME == ISERDESE2}}]]"
)
class _StandaloneBase(MiniSoC, AMPSoC): class _StandaloneBase(MiniSoC, AMPSoC):
mem_map = { mem_map = {
"cri_con": 0x10000000, "cri_con": 0x10000000,
@ -114,6 +125,7 @@ class _StandaloneBase(MiniSoC, AMPSoC):
def add_rtio(self, rtio_channels): def add_rtio(self, rtio_channels):
self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk) self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
self.csr_devices.append("rtio_crg") self.csr_devices.append("rtio_crg")
fix_serdes_timing_path(self.platform)
self.submodules.rtio_core = rtio.Core(rtio_channels) self.submodules.rtio_core = rtio.Core(rtio_channels)
self.csr_devices.append("rtio_core") self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator() self.submodules.rtio = rtio.KernelInitiator()
@ -136,15 +148,6 @@ class _StandaloneBase(MiniSoC, AMPSoC):
self.get_native_sdram_if()) self.get_native_sdram_if())
self.csr_devices.append("rtio_analyzer") self.csr_devices.append("rtio_analyzer")
# ignore timing of path from OSERDESE2 through the pad to ISERDESE2
self.platform.add_platform_command(
"set_false_path -quiet "
"-through [get_pins -filter {{REF_PIN_NAME == OQ || REF_PIN_NAME == TQ}} "
"-of [get_cells -filter {{REF_NAME == OSERDESE2}}]] "
"-to [get_pins -filter {{REF_PIN_NAME == D}} "
"-of [get_cells -filter {{REF_NAME == ISERDESE2}}]]"
)
def _eem_signal(i): def _eem_signal(i):
n = "d{}".format(i) n = "d{}".format(i)
@ -686,6 +689,7 @@ class _MasterBase(MiniSoC, AMPSoC):
self.crg.cd_sys.clk, gtp.rxoutclk) self.crg.cd_sys.clk, gtp.rxoutclk)
self.submodules.rtio_clkmul = _RTIOClockMultiplier(rtio_clk_freq) self.submodules.rtio_clkmul = _RTIOClockMultiplier(rtio_clk_freq)
fix_serdes_timing_path(platform)
def add_rtio(self, rtio_channels): def add_rtio(self, rtio_channels):
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
@ -806,6 +810,7 @@ class _SatelliteBase(BaseSoC):
gtp.txoutclk, gtp.rxoutclk) gtp.txoutclk, gtp.rxoutclk)
self.submodules.rtio_clkmul = _RTIOClockMultiplier(rtio_clk_freq) self.submodules.rtio_clkmul = _RTIOClockMultiplier(rtio_clk_freq)
fix_serdes_timing_path(platform)
def add_rtio(self, rtio_channels): def add_rtio(self, rtio_channels):
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)