From 5f737bef764c3423f5d14185a1f62b8682e76541 Mon Sep 17 00:00:00 2001
From: Robert Jordens <rj@m-labs.hk>
Date: Wed, 12 Oct 2016 14:03:08 +0200
Subject: [PATCH] phaser: 500 MHz dacclock

---
 artiq/examples/phaser/repository/dac_setup.py |  8 ++++----
 artiq/examples/phaser/startup_kernel.py       | 12 ++++++++----
 2 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/artiq/examples/phaser/repository/dac_setup.py b/artiq/examples/phaser/repository/dac_setup.py
index 46577e95d..de7d7a6da 100644
--- a/artiq/examples/phaser/repository/dac_setup.py
+++ b/artiq/examples/phaser/repository/dac_setup.py
@@ -20,9 +20,9 @@ ts = JESD204BTransportSettings(
 jesd_settings = JESD204BSettings(ps, ts, did=0x5a, bid=0x5)
 jesd_checksum = jesd_settings.get_configuration_checksum()
 # external clk=2000MHz
-# pclock=250MHz
-# deviceclock_fpga=500MHz
-# deviceclock_dac=2000MHz
+# pclock=125MHz
+# deviceclock_fpga=125MHz
+# deviceclock_dac=500MHz
 
 
 class DACSetup(EnvExperiment):
@@ -98,7 +98,7 @@ class DACSetup(EnvExperiment):
 
         self.ad9154.dac_write(AD9154_SPI_PAGEINDX, 0x3) # A and B dual
 
-        self.ad9154.dac_write(AD9154_INTERP_MODE, 4) # 8x
+        self.ad9154.dac_write(AD9154_INTERP_MODE, 1) # 2x
         self.ad9154.dac_write(AD9154_MIX_MODE, 0)
         self.ad9154.dac_write(AD9154_DATA_FORMAT, AD9154_BINARY_FORMAT_SET(0)) # s16
         self.ad9154.dac_write(AD9154_DATAPATH_CTRL,
diff --git a/artiq/examples/phaser/startup_kernel.py b/artiq/examples/phaser/startup_kernel.py
index 089d49d92..1d2890832 100644
--- a/artiq/examples/phaser/startup_kernel.py
+++ b/artiq/examples/phaser/startup_kernel.py
@@ -42,10 +42,14 @@ class StartupKernel(EnvExperiment):
         self.ad9154.clock_write(AD9516_OUT5, 2*AD9516_OUT5_POWER_DOWN)
         self.ad9154.clock_write(AD9516_OUT8, 1*AD9516_OUT8_POWER_DOWN)
 
-        # DAC deviceclk, clk/1
-        self.ad9154.clock_write(AD9516_DIVIDER_0_2, AD9516_DIVIDER_0_DIRECT_TO_OUTPUT)
-        self.ad9154.clock_write(AD9516_OUT1, 0*AD9516_OUT1_POWER_DOWN |
-                2*AD9516_OUT1_LVPECLDIFFERENTIAL_VOLTAGE)
+        # DAC deviceclk, dclk/1
+        self.ad9154.clock_write(AD9516_DIVIDER_0_1, AD9516_DIVIDER_0_BYPASS)
+        self.ad9154.clock_write(AD9516_DIVIDER_0_2,
+                                0*AD9516_DIVIDER_0_DIRECT_TO_OUTPUT |
+                                0*AD9516_DIVIDER_0_DCCOFF)
+        self.ad9154.clock_write(AD9516_OUT1,
+                                0*AD9516_OUT1_POWER_DOWN |
+                                2*AD9516_OUT1_LVPECLDIFFERENTIAL_VOLTAGE)
 
         # FPGA deviceclk, dclk/4
         self.ad9154.clock_write(AD9516_DIVIDER_4_3, AD9516_DIVIDER_4_BYPASS_2)