mirror of https://github.com/m-labs/artiq.git
rtio: fix FIFO WE
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@ -54,7 +54,7 @@ class RTIO(Module, AutoCSR):
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channel_o.reset.eq(self._r_reset.storage),
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channel_o.event.timestamp.eq(self._r_o_timestamp.storage),
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channel_o.event.value.eq(self._r_o_value.storage),
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channel_o.we.eq(self._r_o_we.re & (self._r_chan_sel == n))
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channel_o.we.eq(self._r_o_we.re & (self._r_chan_sel.storage == n))
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]
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channel_o = Array(channel_os)[self._r_chan_sel.storage]
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