M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 1
Code Issues Projects Releases Wiki Activity

rtio: fix FIFO WE

This commit is contained in:
Sebastien Bourdeauducq 2014-07-20 18:22:53 -06:00
parent 0cb18d58a8
commit 5f58789592
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
soc/artiqlib/rtio/__init__.py
View File

@ -54,7 +54,7 @@ class RTIO(Module, AutoCSR):
channel_o.reset.eq(self._r_reset.storage),
channel_o.event.timestamp.eq(self._r_o_timestamp.storage),
channel_o.event.value.eq(self._r_o_value.storage),
channel_o.we.eq(self._r_o_we.re & (self._r_chan_sel == n))
channel_o.we.eq(self._r_o_we.re & (self._r_chan_sel.storage == n))
]
channel_o = Array(channel_os)[self._r_chan_sel.storage]