From 5df766e6da75c37fd29217e75b7c933e40f87cfc Mon Sep 17 00:00:00 2001 From: SingularitySurfer Date: Tue, 21 Jun 2022 07:36:59 +0000 Subject: [PATCH] fix ors --- artiq/coredevice/phaser.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/artiq/coredevice/phaser.py b/artiq/coredevice/phaser.py index 7d0f87315..b620e653e 100644 --- a/artiq/coredevice/phaser.py +++ b/artiq/coredevice/phaser.py @@ -1058,7 +1058,7 @@ class PhaserChannel: self.trf_write(data) @kernel - def set_servo(self, bypass=1, hold=0, profile=0): + def set_servo(self, profile=0, bypass=1, hold=0): """Set the servo configuration. :param bypass: 1 to enable bypass (default), 0 to engage servo @@ -1068,13 +1068,14 @@ class PhaserChannel: if (profile < 0) or (profile > 3): raise ValueError("invalid profile index") addr = PHASER_ADDR_SERVO_CFG0 + self.index + data = 0 if bypass == 0: data = 1 if hold == 1: - data = data or (1 << 1) + data = data | (1 << 1) if bypass: hold = 1 - data = (profile << 2) or (hold << 1) or (bypass << 0) + data = (profile << 2) | (hold << 1) | (bypass << 0) self.phaser.write8(addr, data) @kernel