mirror of https://github.com/m-labs/artiq.git
parent
e1b0fcc24e
commit
5dbdc5650c
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@ -130,12 +130,15 @@ class SUServo:
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def set_config(self, enable):
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"""Set SU Servo configuration.
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Disabling takes up to 2 Servo cycles (~2.2 µs) to clear
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the processing pipeline.
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This method advances the timeline by one Servo memory access.
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It does not support RTIO event replacement.
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:param enable: Enable Servo operation.
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:param enable (int): Enable Servo operation. Enabling starts servo
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iterations beginning with the ADC sampling stage. This also
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provides a mean for synchronization of Servo updates to other RTIO
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activity.
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Disabling takes up to 2 Servo cycles (~2.2 µs) to clear the
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processing pipeline.
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"""
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self.write(CONFIG_ADDR, enable)
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@ -144,7 +147,16 @@ class SUServo:
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"""Get current SU Servo status.
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This method does not advance the timeline but consumes all slack.
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The ``done`` bit indicates that a SUServo cycle has completed.
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It is pulsed for one RTIO cycle every SUServo cycle and asserted
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continuously when the servo is not ``enabled`` and the pipeline has
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drained (the last DDS update is done).
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This method returns and clears the clip indicator for all channels.
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An asserted clip indicator corresponds to the servo having encountered
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an input signal on an active channel that would have resulted in the
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IIR state exceeding the output range.
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:return: Status. Bit 0: enabled, bit 1: done,
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bits 8-15: channel clip indicators.
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