mirror of https://github.com/m-labs/artiq.git
top.add_constant() -> top.config[] (CSRConstant)
This is to be synchronized with the corresponding change in misoc.
This commit is contained in:
parent
0d90d88eff
commit
5db1f9794e
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@ -111,9 +111,9 @@ class _NIST_QCx(MiniSoC, AMPSoC):
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
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self.submodules.rtio = rtio.RTIO(rtio_channels)
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self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width)
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self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width
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assert self.rtio.fine_ts_width <= 3
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self.add_constant("DDS_RTIO_CLK_RATIO", 8 >> self.rtio.fine_ts_width)
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self.config["DDS_RTIO_CLK_RATIO"] = 8 >> self.rtio.fine_ts_width
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
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@ -167,14 +167,14 @@ class NIST_QC1(_NIST_QCx):
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phy = ttl_simple.Output(platform.request("user_led", 2))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.add_constant("RTIO_REGULAR_TTL_COUNT", len(rtio_channels))
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self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
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phy = ttl_simple.ClockGen(platform.request("ttl", 15))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels))
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self.add_constant("DDS_CHANNEL_COUNT", 8)
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self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels)
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self.config["DDS_CHANNEL_COUNT"] = 8
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self.add_constant("DDS_AD9858")
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phy = dds.AD9858(platform.request("dds"), 8)
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self.submodules += phy
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@ -211,14 +211,14 @@ class NIST_QC2(_NIST_QCx):
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phy = ttl_simple.Output(platform.request("user_led", 2))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.add_constant("RTIO_REGULAR_TTL_COUNT", len(rtio_channels))
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self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
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phy = ttl_simple.ClockGen(platform.request("ttl", 14))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels))
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self.add_constant("DDS_CHANNEL_COUNT", 11)
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self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels)
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self.config["DDS_CHANNEL_COUNT"] = 11
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self.add_constant("DDS_AD9914")
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self.add_constant("DDS_ONEHOT_SEL")
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phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
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@ -173,14 +173,14 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4))
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self.add_constant("RTIO_REGULAR_TTL_COUNT", len(rtio_channels))
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self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
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phy = ttl_simple.ClockGen(platform.request("ttl", 15))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels))
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self.add_constant("DDS_CHANNEL_COUNT", 8)
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self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels)
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self.config["DDS_CHANNEL_COUNT"] = 8
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self.add_constant("DDS_AD9858")
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dds_pins = platform.request("dds")
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self.comb += dds_pins.p.eq(0)
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@ -192,8 +192,8 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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# RTIO core
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self.submodules.rtio = rtio.RTIO(rtio_channels)
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self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width)
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self.add_constant("DDS_RTIO_CLK_RATIO", 8 >> self.rtio.fine_ts_width)
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self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width
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self.config["DDS_RTIO_CLK_RATIO"] = 8 >> self.rtio.fine_ts_width
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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# CPU connections
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@ -5,11 +5,11 @@
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#include "dds.h"
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#include "bridge.h"
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#define TIME_BUFFER (8000 << RTIO_FINE_TS_WIDTH)
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#define TIME_BUFFER (8000 << CONFIG_RTIO_FINE_TS_WIDTH)
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static void dds_write(int addr, int data)
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{
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rtio_chan_sel_write(RTIO_DDS_CHANNEL);
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rtio_chan_sel_write(CONFIG_RTIO_DDS_CHANNEL);
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rtio_o_address_write(addr);
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rtio_o_data_write(data);
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rtio_o_timestamp_write(rtio_get_counter() + TIME_BUFFER);
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@ -20,7 +20,7 @@ long long int clock_get_ms(void)
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timer0_update_value_write(1);
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clock_sys = 0x7fffffffffffffffLL - timer0_value_read();
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clock_ms = clock_sys/(SYSTEM_CLOCK_FREQUENCY/1000);
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clock_ms = clock_sys/(CONFIG_CLOCK_FREQUENCY/1000);
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return clock_ms;
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}
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@ -29,7 +29,7 @@ void busywait_us(long long int us)
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long long int threshold;
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timer0_update_value_write(1);
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threshold = timer0_value_read() - us*SYSTEM_CLOCK_FREQUENCY/1000000LL;
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threshold = timer0_value_read() - us*CONFIG_CLOCK_FREQUENCY/1000000LL;
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while(timer0_value_read() > threshold)
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timer0_update_value_write(1);
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}
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@ -6,7 +6,7 @@
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#include "log.h"
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#include "dds.h"
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#define DURATION_WRITE (5 << RTIO_FINE_TS_WIDTH)
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#define DURATION_WRITE (5 << CONFIG_RTIO_FINE_TS_WIDTH)
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#if defined DDS_AD9858
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/* Assume 8-bit bus */
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@ -16,7 +16,7 @@
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#elif defined DDS_AD9914
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/* Assume 16-bit bus */
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/* DAC calibration takes max. 1ms as per datasheet */
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#define DURATION_DAC_CAL (147000 << RTIO_FINE_TS_WIDTH)
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#define DURATION_DAC_CAL (147000 << CONFIG_RTIO_FINE_TS_WIDTH)
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/* not counting final FUD */
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#define DURATION_INIT (8*DURATION_WRITE + DURATION_DAC_CAL)
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#define DURATION_PROGRAM (6*DURATION_WRITE) /* not counting FUD */
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@ -29,7 +29,7 @@
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rtio_o_address_write(addr); \
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rtio_o_data_write(data); \
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rtio_o_timestamp_write(now); \
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rtio_write_and_process_status(now, RTIO_DDS_CHANNEL); \
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rtio_write_and_process_status(now, CONFIG_RTIO_DDS_CHANNEL); \
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now += DURATION_WRITE; \
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} while(0)
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@ -37,7 +37,7 @@ void dds_init(long long int timestamp, int channel)
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{
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long long int now;
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rtio_chan_sel_write(RTIO_DDS_CHANNEL);
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rtio_chan_sel_write(CONFIG_RTIO_DDS_CHANNEL);
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now = timestamp - DURATION_INIT;
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@ -87,14 +87,14 @@ void dds_init(long long int timestamp, int channel)
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/* Compensation to keep phase continuity when switching from absolute or tracking
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* to continuous phase mode. */
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static unsigned int continuous_phase_comp[DDS_CHANNEL_COUNT];
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static unsigned int continuous_phase_comp[CONFIG_DDS_CHANNEL_COUNT];
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static void dds_set_one(long long int now, long long int ref_time, unsigned int channel,
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unsigned int ftw, unsigned int pow, int phase_mode, unsigned int amplitude)
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{
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unsigned int channel_enc;
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if(channel >= DDS_CHANNEL_COUNT) {
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if(channel >= CONFIG_DDS_CHANNEL_COUNT) {
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log("Attempted to set invalid DDS channel");
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return;
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}
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@ -118,7 +118,7 @@ static void dds_set_one(long long int now, long long int ref_time, unsigned int
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#endif
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/* We need the RTIO fine timestamp clock to be phase-locked
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* to DDS SYSCLK, and divided by an integer DDS_RTIO_CLK_RATIO.
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* to DDS SYSCLK, and divided by an integer CONFIG_DDS_RTIO_CLK_RATIO.
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*/
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if(phase_mode == PHASE_MODE_CONTINUOUS) {
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/* Do not clear phase accumulator on FUD */
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@ -142,9 +142,9 @@ static void dds_set_one(long long int now, long long int ref_time, unsigned int
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DDS_WRITE(DDS_CFR1L, 0x2108);
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#endif
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fud_time = now + 2*DURATION_WRITE;
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pow -= (ref_time - fud_time)*DDS_RTIO_CLK_RATIO*ftw >> (32-DDS_POW_WIDTH);
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pow -= (ref_time - fud_time)*CONFIG_DDS_RTIO_CLK_RATIO*ftw >> (32-DDS_POW_WIDTH);
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if(phase_mode == PHASE_MODE_TRACKING)
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pow += ref_time*DDS_RTIO_CLK_RATIO*ftw >> (32-DDS_POW_WIDTH);
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pow += ref_time*CONFIG_DDS_RTIO_CLK_RATIO*ftw >> (32-DDS_POW_WIDTH);
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continuous_phase_comp[channel] = pow;
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}
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@ -190,7 +190,7 @@ void dds_batch_exit(void)
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if(!batch_mode)
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artiq_raise_from_c("DDSBatchError", "DDS batch error", 0, 0, 0);
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rtio_chan_sel_write(RTIO_DDS_CHANNEL);
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rtio_chan_sel_write(CONFIG_RTIO_DDS_CHANNEL);
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/* + FUD time */
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now = batch_ref_time - batch_count*(DURATION_PROGRAM + DURATION_WRITE);
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for(i=0;i<batch_count;i++) {
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@ -216,7 +216,7 @@ void dds_set(long long int timestamp, int channel,
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batch[batch_count].amplitude = amplitude;
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batch_count++;
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} else {
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rtio_chan_sel_write(RTIO_DDS_CHANNEL);
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rtio_chan_sel_write(CONFIG_RTIO_DDS_CHANNEL);
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dds_set_one(timestamp - DURATION_PROGRAM, timestamp, channel, ftw, pow, phase_mode,
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amplitude);
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}
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@ -12,10 +12,10 @@
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#include "log.h"
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#include "flash_storage.h"
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#if (defined CSR_SPIFLASH_BASE && defined SPIFLASH_PAGE_SIZE)
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#if (defined CSR_SPIFLASH_BASE && defined CONFIG_SPIFLASH_PAGE_SIZE)
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#define STORAGE_ADDRESS ((char *)(FLASH_BOOT_ADDRESS + 256*1024))
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#define STORAGE_SIZE SPIFLASH_SECTOR_SIZE
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#define STORAGE_SIZE CONFIG_SPIFLASH_SECTOR_SIZE
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#define END_MARKER (0xFFFFFFFF)
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#define min(a, b) (a>b?b:a)
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@ -302,4 +302,4 @@ void fs_remove(const char *key)
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fs_write(key, NULL, 0);
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}
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#endif /* CSR_SPIFLASH_BASE && SPIFLASH_PAGE_SIZE */
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#endif /* CSR_SPIFLASH_BASE && CONFIG_SPIFLASH_PAGE_SIZE */
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@ -90,7 +90,7 @@ void kloader_start_kernel()
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static int kloader_start_flash_kernel(char *key)
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{
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#if (defined CSR_SPIFLASH_BASE && defined SPIFLASH_PAGE_SIZE)
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#if (defined CSR_SPIFLASH_BASE && defined CONFIG_SPIFLASH_PAGE_SIZE)
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char buffer[32*1024];
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unsigned int length, remain;
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@ -268,7 +268,7 @@ long long int now_init(void)
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if(now < 0) {
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rtio_init();
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now = rtio_get_counter() + (272000 << RTIO_FINE_TS_WIDTH);
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now = rtio_get_counter() + (272000 << CONFIG_RTIO_FINE_TS_WIDTH);
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}
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return now;
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@ -64,14 +64,14 @@ static int hex2nib(int c)
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static void init_macadr(void)
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{
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static const unsigned char default_macadr[6] = {0x10, 0xe2, 0xd5, 0x32, 0x50, 0x00};
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#if (defined CSR_SPIFLASH_BASE && defined SPIFLASH_PAGE_SIZE)
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#if (defined CSR_SPIFLASH_BASE && defined CONFIG_SPIFLASH_PAGE_SIZE)
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char b[32];
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char fs_macadr[6];
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int i, r, s;
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#endif
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memcpy(macadr, default_macadr, 6);
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#if (defined CSR_SPIFLASH_BASE && defined SPIFLASH_PAGE_SIZE)
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#if (defined CSR_SPIFLASH_BASE && defined CONFIG_SPIFLASH_PAGE_SIZE)
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r = fs_read("mac", b, sizeof(b) - 1, NULL);
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if(r <= 0)
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return;
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@ -93,12 +93,12 @@ static void init_macadr(void)
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static void fsip_or_default(struct ip4_addr *d, char *key, int i1, int i2, int i3, int i4)
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{
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int r;
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#if (defined CSR_SPIFLASH_BASE && defined SPIFLASH_PAGE_SIZE)
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#if (defined CSR_SPIFLASH_BASE && defined CONFIG_SPIFLASH_PAGE_SIZE)
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char cp[32];
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#endif
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IP4_ADDR(d, i1, i2, i3, i4);
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#if (defined CSR_SPIFLASH_BASE && defined SPIFLASH_PAGE_SIZE)
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#if (defined CSR_SPIFLASH_BASE && defined CONFIG_SPIFLASH_PAGE_SIZE)
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r = fs_read(key, cp, sizeof(cp) - 1, NULL);
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if(r <= 0)
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return;
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@ -39,7 +39,7 @@ struct monitor_reply {
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long long int ttl_levels;
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long long int ttl_oes;
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long long int ttl_overrides;
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unsigned int dds_ftws[DDS_CHANNEL_COUNT];
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unsigned int dds_ftws[CONFIG_DDS_CHANNEL_COUNT];
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};
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static void moninj_monitor(const ip_addr_t *addr, u16_t port)
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@ -51,7 +51,7 @@ static void moninj_monitor(const ip_addr_t *addr, u16_t port)
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reply.ttl_levels = 0;
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reply.ttl_oes = 0;
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reply.ttl_overrides = 0;
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for(i=0;i<RTIO_REGULAR_TTL_COUNT;i++) {
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for(i=0;i<CONFIG_RTIO_REGULAR_TTL_COUNT;i++) {
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rtio_moninj_mon_chan_sel_write(i);
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rtio_moninj_mon_probe_sel_write(0);
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rtio_moninj_mon_value_update_write(1);
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@ -67,8 +67,8 @@ static void moninj_monitor(const ip_addr_t *addr, u16_t port)
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reply.ttl_overrides |= 1LL << i;
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}
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rtio_moninj_mon_chan_sel_write(RTIO_DDS_CHANNEL);
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for(i=0;i<DDS_CHANNEL_COUNT;i++) {
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rtio_moninj_mon_chan_sel_write(CONFIG_RTIO_DDS_CHANNEL);
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for(i=0;i<CONFIG_DDS_CHANNEL_COUNT;i++) {
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rtio_moninj_mon_probe_sel_write(i);
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rtio_moninj_mon_value_update_write(1);
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reply.dds_ftws[i] = rtio_moninj_mon_value_read();
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@ -432,7 +432,7 @@ static int process_input(void)
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break;
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case REMOTEMSG_TYPE_FLASH_READ_REQUEST: {
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#if SPIFLASH_SECTOR_SIZE - 4 > BUFFER_OUT_SIZE - 9
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#if CONFIG_SPIFLASH_SECTOR_SIZE - 4 > BUFFER_OUT_SIZE - 9
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#error Output buffer cannot hold the flash storage data
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#endif
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const char *key = in_packet_string();
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@ -447,7 +447,7 @@ static int process_input(void)
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}
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case REMOTEMSG_TYPE_FLASH_WRITE_REQUEST: {
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#if SPIFLASH_SECTOR_SIZE - 4 > BUFFER_IN_SIZE - 9
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#if CONFIG_SPIFLASH_SECTOR_SIZE - 4 > BUFFER_IN_SIZE - 9
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#error Input buffer cannot hold the flash storage data
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#endif
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const char *key, *value;
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@ -330,15 +330,15 @@ static void ddstest(char *n, char *channel)
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do_ddstest_one(channel2);
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} else {
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for(i=0;i<n2;i++)
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for(j=0;j<DDS_CHANNEL_COUNT;j++)
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for(j=0;j<CONFIG_DDS_CHANNEL_COUNT;j++)
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do_ddstest_one(j);
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}
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}
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#if (defined CSR_SPIFLASH_BASE && defined SPIFLASH_PAGE_SIZE)
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#if (defined CSR_SPIFLASH_BASE && defined CONFIG_SPIFLASH_PAGE_SIZE)
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static void fsread(char *key)
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{
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char readbuf[SPIFLASH_SECTOR_SIZE];
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char readbuf[CONFIG_SPIFLASH_SECTOR_SIZE];
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int r;
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r = fs_read(key, readbuf, sizeof(readbuf)-1, NULL);
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@ -361,13 +361,13 @@ static void fsfull(void)
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char value[4096];
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memset(value, '@', sizeof(value));
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for(i = 0; i < SPIFLASH_SECTOR_SIZE/sizeof(value); i++)
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for(i = 0; i < CONFIG_SPIFLASH_SECTOR_SIZE/sizeof(value); i++)
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fs_write("plip", value, sizeof(value));
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}
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static void check_read(char *key, char *expected, unsigned int length, unsigned int testnum)
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{
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char readbuf[SPIFLASH_SECTOR_SIZE];
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char readbuf[CONFIG_SPIFLASH_SECTOR_SIZE];
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unsigned int remain, readlength;
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memset(readbuf, '\0', sizeof(readbuf));
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@ -417,7 +417,7 @@ static inline void test_sector_is_full(void)
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fs_erase();
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memset(value, '@', sizeof(value));
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for(c = 1; c <= SPIFLASH_SECTOR_SIZE/sizeof(value); c++) {
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for(c = 1; c <= CONFIG_SPIFLASH_SECTOR_SIZE/sizeof(value); c++) {
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key[0] = c;
|
||||
check_write(fs_write(key, value, sizeof(value) - 6));
|
||||
}
|
||||
|
@ -427,7 +427,7 @@ static inline void test_sector_is_full(void)
|
|||
|
||||
static void test_one_big_record(int testnum)
|
||||
{
|
||||
char value[SPIFLASH_SECTOR_SIZE];
|
||||
char value[CONFIG_SPIFLASH_SECTOR_SIZE];
|
||||
memset(value, '@', sizeof(value));
|
||||
|
||||
fs_erase();
|
||||
|
@ -450,12 +450,12 @@ static void test_one_big_record(int testnum)
|
|||
|
||||
static void test_flush_duplicate_rollback(int testnum)
|
||||
{
|
||||
char value[SPIFLASH_SECTOR_SIZE];
|
||||
char value[CONFIG_SPIFLASH_SECTOR_SIZE];
|
||||
memset(value, '@', sizeof(value));
|
||||
|
||||
fs_erase();
|
||||
/* This makes the flash storage full with one big record */
|
||||
check_write(fs_write("a", value, SPIFLASH_SECTOR_SIZE - 6));
|
||||
check_write(fs_write("a", value, CONFIG_SPIFLASH_SECTOR_SIZE - 6));
|
||||
/* This should trigger the try_to_flush_duplicate code which
|
||||
* at first will not keep the old "a" record value because we are
|
||||
* overwriting it. But then it should roll back to the old value
|
||||
|
@ -465,12 +465,12 @@ static void test_flush_duplicate_rollback(int testnum)
|
|||
check_write(!fs_write("a", value, sizeof(value)));
|
||||
/* check we still have the old record value */
|
||||
value[0] = '@';
|
||||
check_read("a", value, SPIFLASH_SECTOR_SIZE - 6, testnum);
|
||||
check_read("a", value, CONFIG_SPIFLASH_SECTOR_SIZE - 6, testnum);
|
||||
}
|
||||
|
||||
static void test_too_big_fails(int testnum)
|
||||
{
|
||||
char value[SPIFLASH_SECTOR_SIZE];
|
||||
char value[CONFIG_SPIFLASH_SECTOR_SIZE];
|
||||
memset(value, '@', sizeof(value));
|
||||
|
||||
fs_erase();
|
||||
|
@ -551,7 +551,7 @@ static void help(void)
|
|||
puts("ddsftw <n> <d> - write FTW");
|
||||
puts("ddstest <n> <c> - perform test sequence on DDS");
|
||||
puts("leds <n> - set LEDs");
|
||||
#if (defined CSR_SPIFLASH_BASE && defined SPIFLASH_PAGE_SIZE)
|
||||
#if (defined CSR_SPIFLASH_BASE && defined CONFIG_SPIFLASH_PAGE_SIZE)
|
||||
puts("fserase - erase flash storage");
|
||||
puts("fswrite <k> <v> - write to flash storage");
|
||||
puts("fsread <k> - read flash storage");
|
||||
|
@ -633,7 +633,7 @@ static void do_command(char *c)
|
|||
else if(strcmp(token, "ddsftw") == 0) ddsftw(get_token(&c), get_token(&c));
|
||||
else if(strcmp(token, "ddstest") == 0) ddstest(get_token(&c), get_token(&c));
|
||||
|
||||
#if (defined CSR_SPIFLASH_BASE && defined SPIFLASH_PAGE_SIZE)
|
||||
#if (defined CSR_SPIFLASH_BASE && defined CONFIG_SPIFLASH_PAGE_SIZE)
|
||||
else if(strcmp(token, "fserase") == 0) fs_erase();
|
||||
else if(strcmp(token, "fswrite") == 0) fswrite(get_token(&c), c, strlen(c));
|
||||
else if(strcmp(token, "fsread") == 0) fsread(get_token(&c));
|
||||
|
|
Loading…
Reference in New Issue