mirror of https://github.com/m-labs/artiq.git
runtime: refactor rt2wb/dds
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parent
d3c94827eb
commit
5dae9f8aa8
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@ -7,7 +7,7 @@ OBJECTS := isr.o clock.o rtiocrg.o flash_storage.o mailbox.o \
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session.o log.o analyzer.o moninj.o net_server.o bridge_ctl.o \
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ksupport_data.o kloader.o test_mode.o main.o
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OBJECTS_KSUPPORT := ksupport.o artiq_personality.o mailbox.o \
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bridge.o rtio.o ttl.o dds.o rt2wb.o
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bridge.o rtio.o ttl.o rt2wb.o dds.o
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CFLAGS += -I$(LIBALLOC_DIRECTORY) \
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-I$(MISOC_DIRECTORY)/software/include/dyld \
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@ -2,7 +2,7 @@
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#include <stdio.h>
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#include "artiq_personality.h"
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#include "rtio.h"
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#include "rt2wb.h"
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#include "log.h"
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#include "dds.h"
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@ -26,10 +26,7 @@
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#endif
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#define DDS_WRITE(addr, data) do { \
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rtio_o_address_write(addr); \
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rtio_o_data_write(data); \
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rtio_o_timestamp_write(now); \
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rtio_write_and_process_status(now, CONFIG_RTIO_DDS_CHANNEL); \
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rt2wb_write(now, CONFIG_RTIO_DDS_CHANNEL, addr, data); \
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now += DURATION_WRITE; \
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} while(0)
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@ -37,8 +34,6 @@ void dds_init(long long int timestamp, int channel)
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{
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long long int now;
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rtio_chan_sel_write(CONFIG_RTIO_DDS_CHANNEL);
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now = timestamp - DURATION_INIT;
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#ifdef CONFIG_DDS_ONEHOT_SEL
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@ -94,10 +89,10 @@ static void dds_set_one(long long int now, long long int ref_time, unsigned int
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{
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unsigned int channel_enc;
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if(channel >= CONFIG_DDS_CHANNEL_COUNT) {
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core_log("Attempted to set invalid DDS channel\n");
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return;
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}
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if(channel >= CONFIG_DDS_CHANNEL_COUNT) {
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core_log("Attempted to set invalid DDS channel\n");
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return;
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}
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#ifdef CONFIG_DDS_ONEHOT_SEL
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channel_enc = 1 << channel;
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#else
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@ -190,7 +185,6 @@ void dds_batch_exit(void)
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if(!batch_mode)
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artiq_raise_from_c("DDSBatchError", "DDS batch error", 0, 0, 0);
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rtio_chan_sel_write(CONFIG_RTIO_DDS_CHANNEL);
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/* + FUD time */
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now = batch_ref_time - batch_count*(DURATION_PROGRAM + DURATION_WRITE);
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for(i=0;i<batch_count;i++) {
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@ -216,7 +210,6 @@ void dds_set(long long int timestamp, int channel,
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batch[batch_count].amplitude = amplitude;
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batch_count++;
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} else {
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rtio_chan_sel_write(CONFIG_RTIO_DDS_CHANNEL);
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dds_set_one(timestamp - DURATION_PROGRAM, timestamp, channel, ftw, pow, phase_mode,
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amplitude);
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}
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@ -8,40 +8,16 @@
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void rt2wb_write(long long int timestamp, int channel, int addr,
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unsigned int data)
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{
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rtio_chan_sel_write(channel);
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rtio_o_address_write(addr);
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rtio_o_data_write(data);
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rtio_o_timestamp_write(timestamp);
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rtio_write_and_process_status(timestamp, channel);
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rtio_output(timestamp, channel, addr, data);
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}
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unsigned int rt2wb_read_sync(long long int timestamp, int channel,
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int addr, int duration)
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unsigned int rt2wb_read_sync(long long int timestamp, int channel, int addr,
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int duration)
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{
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int status;
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unsigned int data;
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rt2wb_write(timestamp, channel, addr, 0);
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while((status = rtio_i_status_read())) {
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if(status & RTIO_I_STATUS_OVERFLOW) {
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rtio_i_overflow_reset_write(1);
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artiq_raise_from_c("RTIOOverflow",
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"RT2WB overflow on channel {0}",
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channel, 0, 0);
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}
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if(rtio_get_counter() >= timestamp + duration) {
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/* check empty flag again to prevent race condition.
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* now we are sure that the time limit has been exceeded.
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*/
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if(rtio_i_status_read() & RTIO_I_STATUS_EMPTY)
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artiq_raise_from_c("InternalError",
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"RT2WB read failed on channel {0}",
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channel, 0, 0);
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}
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/* input FIFO is empty - keep waiting */
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}
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rtio_output(timestamp, channel, addr, 0);
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rtio_input_wait(timestamp + duration, channel);
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data = rtio_i_data_read();
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rtio_i_re_write(1);
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return data;
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@ -1,6 +1,8 @@
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#ifndef __RT2WB_H
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#define __RT2WB_H
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#include "rtio.h"
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void rt2wb_write(long long int timestamp, int channel, int address,
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unsigned int data);
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unsigned int rt2wb_read_sync(long long int timestamp, int channel, int address,
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@ -39,6 +39,44 @@ void rtio_process_exceptional_status(int status, long long int timestamp, int ch
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}
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}
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void rtio_output(long long int timestamp, int channel, unsigned int addr,
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unsigned int data)
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{
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rtio_chan_sel_write(channel);
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rtio_o_timestamp_write(timestamp);
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rtio_o_address_write(addr);
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rtio_o_data_write(data);
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rtio_write_and_process_status(timestamp, channel);
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}
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void rtio_input_wait(long long int timeout, int channel)
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{
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int status;
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rtio_chan_sel_write(channel);
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while((status = rtio_i_status_read())) {
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if(status & RTIO_I_STATUS_OVERFLOW) {
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rtio_i_overflow_reset_write(1);
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artiq_raise_from_c("RTIOOverflow",
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"RTIO input overflow on channel {0}",
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channel, 0, 0);
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}
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if(rtio_get_counter() >= timeout) {
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/* check empty flag again to prevent race condition.
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* now we are sure that the time limit has been exceeded.
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*/
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if(rtio_i_status_read() & RTIO_I_STATUS_EMPTY)
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artiq_raise_from_c("InternalError",
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"RTIO input timeout on channel {0}",
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channel, 0, 0);
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}
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/* input FIFO is empty - keep waiting */
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}
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}
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void rtio_log_va(long long int timestamp, const char *fmt, va_list args)
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{
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// This executes on the kernel CPU's stack, which is specifically designed
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@ -17,6 +17,9 @@ long long int rtio_get_counter(void);
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void rtio_process_exceptional_status(int status, long long int timestamp, int channel);
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void rtio_log(long long int timestamp, const char *format, ...);
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void rtio_log_va(long long int timestamp, const char *format, va_list args);
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void rtio_output(long long int timestamp, int channel, unsigned int address,
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unsigned int data);
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void rtio_input_wait(long long int timeout, int channel);
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static inline void rtio_write_and_process_status(long long int timestamp, int channel)
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{
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