diff --git a/artiq/gateware/drtio/transceiver/gtx_7series.py b/artiq/gateware/drtio/transceiver/gtx_7series.py
index 2c5897a91..958e1d541 100644
--- a/artiq/gateware/drtio/transceiver/gtx_7series.py
+++ b/artiq/gateware/drtio/transceiver/gtx_7series.py
@@ -11,9 +11,8 @@ class GTX_20X(Module):
     # The transceiver clock on clock_pads must be at the RTIO clock
     # frequency when clock_div2=False, and 2x that frequency when
     # clock_div2=True.
-    def __init__(self, platform,
-                 clock_pads, tx_pads, rx_pads,
-                 sys_clk_freq, clock_div2=False):
+    def __init__(self, clock_pads, tx_pads, rx_pads, sys_clk_freq,
+                 clock_div2=False):
         self.submodules.encoder = ClockDomainsRenamer("rtio")(
             Encoder(2, True))
         self.decoders = [ClockDomainsRenamer("rtio_rx")(
@@ -22,6 +21,11 @@ class GTX_20X(Module):
 
         self.rx_ready = Signal()
 
+        # transceiver direct clock outputs
+        # useful to specify clock constraints in a way palatable to Vivado
+        self.txoutclk = Signal()
+        self.rxoutclk = Signal()
+
         # # #
 
         refclk = Signal()
@@ -50,9 +54,7 @@ class GTX_20X(Module):
         self.comb += tx_init.cplllock.eq(cplllock), \
                      rx_init.cplllock.eq(cplllock)
 
-        txoutclk = Signal()
         txdata = Signal(20)
-        rxoutclk = Signal()
         rxdata = Signal(20)
         self.specials += \
             Instance("GTXE2_CHANNEL",
@@ -88,7 +90,7 @@ class GTX_20X(Module):
                 # TX clock
                 p_TXBUF_EN="FALSE",
                 p_TX_XCLK_SEL="TXUSR",
-                o_TXOUTCLK=txoutclk,
+                o_TXOUTCLK=self.txoutclk,
                 i_TXSYSCLKSEL=0b00,
                 i_TXOUTCLKSEL=0b11,
 
@@ -134,7 +136,7 @@ class GTX_20X(Module):
                 i_RXDDIEN=1,
                 i_RXSYSCLKSEL=0b00,
                 i_RXOUTCLKSEL=0b010,
-                o_RXOUTCLK=rxoutclk,
+                o_RXOUTCLK=self.rxoutclk,
                 i_RXUSRCLK=ClockSignal("rtio_rx"),
                 i_RXUSRCLK2=ClockSignal("rtio_rx"),
                 p_RXCDR_CFG=0x03000023FF10100020,
@@ -165,7 +167,7 @@ class GTX_20X(Module):
         self.sync += tx_reset_deglitched.eq(~tx_init.done)
         self.clock_domains.cd_rtio = ClockDomain()
         self.specials += [
-            Instance("BUFG", i_I=txoutclk, o_O=self.cd_rtio.clk),
+            Instance("BUFG", i_I=self.txoutclk, o_O=self.cd_rtio.clk),
             AsyncResetSynchronizer(self.cd_rtio, tx_reset_deglitched)
         ]
         rx_reset_deglitched = Signal()
@@ -173,12 +175,9 @@ class GTX_20X(Module):
         self.sync.rtio += rx_reset_deglitched.eq(~rx_init.done)
         self.clock_domains.cd_rtio_rx = ClockDomain()
         self.specials += [
-            Instance("BUFG", i_I=rxoutclk, o_O=self.cd_rtio_rx.clk),
+            Instance("BUFG", i_I=self.rxoutclk, o_O=self.cd_rtio_rx.clk),
             AsyncResetSynchronizer(self.cd_rtio_rx, rx_reset_deglitched)
         ]
-        platform.add_period_constraint(txoutclk, 1e9/self.rtio_clk_freq)
-        platform.add_period_constraint(rxoutclk, 1e9/self.rtio_clk_freq)
-        platform.add_false_path_constraints(txoutclk, rxoutclk)
 
         self.comb += [
             txdata.eq(Cat(self.encoder.output[0], self.encoder.output[1])),
diff --git a/artiq/gateware/targets/kc705_drtio_master.py b/artiq/gateware/targets/kc705_drtio_master.py
index 4f0ed088b..8459c2ff4 100755
--- a/artiq/gateware/targets/kc705_drtio_master.py
+++ b/artiq/gateware/targets/kc705_drtio_master.py
@@ -59,7 +59,6 @@ class Master(MiniSoC, AMPSoC):
             # GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
             # simple TTLs
             self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10(
-                platform=platform,
                 clock_pads=platform.request("sgmii_clock"),
                 tx_pads=tx_pads,
                 rx_pads=rx_pads,
@@ -70,7 +69,6 @@ class Master(MiniSoC, AMPSoC):
             # with SAWG on local RTIO and AD9154-FMC-EBZ
             platform.register_extension(fmc_clock_io)
             self.submodules.transceiver = gtx_7series.GTX_3G(
-                platform=platform,
                 clock_pads=platform.request("ad9154_refclk"),
                 tx_pads=tx_pads,
                 rx_pads=rx_pads,
@@ -80,6 +78,13 @@ class Master(MiniSoC, AMPSoC):
         self.submodules.drtio = DRTIOMaster(self.transceiver)
         self.csr_devices.append("drtio")
 
+        rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq
+        platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period)
+        platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period)
+        platform.add_false_path_constraints(
+            self.crg.cd_sys.clk,
+            self.transceiver.txoutclk, self.transceiver.rxoutclk)
+
         rtio_channels = []
         for i in range(8):
             phy = ttl_simple.Output(platform.request("user_led", i))
diff --git a/artiq/gateware/targets/kc705_drtio_satellite.py b/artiq/gateware/targets/kc705_drtio_satellite.py
index f331c6dca..ee4a2163a 100755
--- a/artiq/gateware/targets/kc705_drtio_satellite.py
+++ b/artiq/gateware/targets/kc705_drtio_satellite.py
@@ -165,7 +165,6 @@ class Satellite(Module):
             # GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
             # simple TTLs
             self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10(
-                platform=platform,
                 clock_pads=platform.request("sgmii_clock"),
                 tx_pads=tx_pads,
                 rx_pads=rx_pads,
@@ -176,7 +175,6 @@ class Satellite(Module):
             # with SAWG on local RTIO and AD9154-FMC-EBZ
             platform.register_extension(fmc_clock_io)
             self.submodules.transceiver = gtx_7series.GTX_3G(
-                platform=platform,
                 clock_pads=platform.request("ad9154_refclk"),
                 tx_pads=tx_pads,
                 rx_pads=rx_pads,
@@ -188,6 +186,14 @@ class Satellite(Module):
         self.submodules.drtio = DRTIOSatellite(
             self.transceiver, self.rx_synchronizer, rtio_channels)
 
+        rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq
+        platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period)
+        platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period)
+        platform.add_false_path_constraints(
+            sys_clock_pads,
+            self.transceiver.txoutclk, self.transceiver.rxoutclk)
+
+
     def build(self, *args, **kwargs):
         self.platform.build(self, *args, **kwargs)