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https://github.com/m-labs/artiq.git
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rtio_clocking: switch clocks and reboot
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f8eb695c0f
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@ -1,8 +1,10 @@
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use board_misoc::config;
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#[cfg(si5324_as_synthesizer)]
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use board_artiq::si5324;
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#[cfg(any(soc_platform = "kasli", has_drtio))]
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use board_misoc::csr;
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#[cfg(has_drtio)]
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use board_misoc::{csr, clock};
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use board_misoc::clock;
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#[derive(Debug, PartialEq)]
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#[allow(non_camel_case_types)]
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@ -54,9 +56,9 @@ fn get_rtio_clock_cfg() -> RtioClock {
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return RtioClock::Ext0_Synth0_125to125;
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#[cfg(all(rtio_frequency = "125.0", not(si5324_ext_ref)))]
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return RtioClock::Int_125;
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#[cfg(all(rtio_frequency = "150.0", not(si5324_ext_ref)))]
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#[cfg(all(rtio_frequency = "150.0", not(si5324_ext_ref), not(soc_platform = "kasli")))]
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return RtioClock::Int_150;
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#[cfg(all(rtio_frequency = "100.0", not(si5324_ext_ref)))]
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#[cfg(all(rtio_frequency = "100.0", not(si5324_ext_ref), not(soc_platform = "kasli")))]
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return RtioClock::Int_100;
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//in case nothing is set
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return RtioClock::Int_125;
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@ -134,7 +136,7 @@ fn setup_si5324_as_synthesizer(cfg: RtioClock) {
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}
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},
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RtioClock::Ext0_Synth0_100to125 => { // 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth
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info!("using 10MHz reference to make 125MHz RTIO clock with PLL");
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info!("using 100MHz reference to make 125MHz RTIO clock with PLL");
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si5324::FrequencySettings {
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n1_hs : 10,
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nc1_ls : 4,
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@ -147,7 +149,7 @@ fn setup_si5324_as_synthesizer(cfg: RtioClock) {
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}
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},
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RtioClock::Ext0_Synth0_125to125 => { // 125MHz output, from 125MHz CLKINx reference, 606 Hz loop bandwidth
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info!("using 10MHz reference to make 125MHz RTIO clock with PLL");
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info!("using 125MHz reference to make 125MHz RTIO clock with PLL");
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si5324::FrequencySettings {
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n1_hs : 5,
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nc1_ls : 8,
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@ -197,7 +199,7 @@ fn setup_si5324_as_synthesizer(cfg: RtioClock) {
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bwsel : 4,
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crystal_ref: true
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}
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}
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},
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_ => { // 125MHz output like above, default (if chosen option is not supported)
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warn!("rtio_clock setting '{:?}' is not supported. Falling back to default internal 125MHz RTIO clock.", cfg);
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si5324::FrequencySettings {
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@ -225,26 +227,50 @@ fn setup_si5324_as_synthesizer(cfg: RtioClock) {
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si5324::setup(&si5324_settings, si5324_ref_input).expect("cannot initialize Si5324");
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}
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#[cfg(si5324_as_synthesizer)]
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fn setup_si5324(clock_cfg: RtioClock) {
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#[cfg(soc_platform = "kasli")]
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{
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let switched = unsafe {
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csr::crg::switch_done_read()
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};
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if switched == 1 {
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info!("Clocking has already been set up.");
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return;
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}
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}
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#[cfg(all(soc_platform = "kasli", hw_rev = "v2.0"))]
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let si5324_ext_input = si5324::Input::Ckin1;
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#[cfg(all(soc_platform = "kasli", not(hw_rev = "v2.0")))]
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let si5324_ext_input = si5324::Input::Ckin2;
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#[cfg(soc_platform = "metlino")]
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let si5324_ext_input = si5324::Input::Ckin2;
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#[cfg(soc_platform = "kc705")]
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let si5324_ext_input = si5324::Input::Ckin2;
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match clock_cfg {
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RtioClock::Ext0_Bypass => {
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info!("using external RTIO clock with PLL bypass");
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si5324::bypass(si5324_ext_input).expect("cannot bypass Si5324")
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},
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_ => setup_si5324_as_synthesizer(clock_cfg),
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}
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// switch sysclk source to si5324
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#[cfg(soc_platform = "kasli")]
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{
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// excessive dots will be cut off by the reboot
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info!("Switching sys clock, rebooting..................");
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unsafe {
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csr::crg::clock_sel_write(1);
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}
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}
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}
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pub fn init() {
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let clock_cfg = get_rtio_clock_cfg();
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#[cfg(si5324_as_synthesizer)]
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{
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#[cfg(all(soc_platform = "kasli", hw_rev = "v2.0"))]
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let si5324_ext_input = si5324::Input::Ckin1;
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#[cfg(all(soc_platform = "kasli", not(hw_rev = "v2.0")))]
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let si5324_ext_input = si5324::Input::Ckin2;
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#[cfg(soc_platform = "metlino")]
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let si5324_ext_input = si5324::Input::Ckin2;
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#[cfg(soc_platform = "kc705")]
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let si5324_ext_input = si5324::Input::Ckin2;
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match clock_cfg {
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RtioClock::Ext0_Bypass => {
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info!("using external RTIO clock with PLL bypass");
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si5324::bypass(si5324_ext_input).expect("cannot bypass Si5324")
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},
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_ => setup_si5324_as_synthesizer(clock_cfg),
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}
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}
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setup_si5324(clock_cfg);
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#[cfg(has_drtio)]
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{
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