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fold comm device into core device

This commit is contained in:
Sebastien Bourdeauducq 2017-05-22 15:45:45 +08:00
parent e7382f4753
commit 5ccca74a3f
20 changed files with 56 additions and 92 deletions
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2
RELEASE_NOTES.rst
View File

@ -36,6 +36,8 @@ Release notes
identifiers (``true``, ``null``, ...) with their Python equivalents
(``True``, ``None` ...).
* Controllers are now named ``aqctl_XXX`` instead of ``XXX_controller``.
* In the device database, the "comm" device has been folded into the "core" device.
Move the "host" argument into the "core" device, and remove the "comm" device.
2.3

28
artiq/coredevice/comm_kernel.py
View File

@ -109,8 +109,34 @@ def initialize_connection(host, port):
return sock
class CommKernelDummy:
def __init__(self):
pass
def switch_clock(self, external):
pass
def load(self, kernel_library):
pass
def run(self):
pass
def serve(self, embedding_map, symbolizer, demangler):
pass
def check_system_info(self):
pass
def get_log(self):
return ""
def clear_log(self):
pass
class CommKernel:
def __init__(self, dmgr, host, port=1381):
def __init__(self, host, port=1381):
self._read_type = None
self.host = host
self.port = port

27
artiq/coredevice/comm_kernel_dummy.py
View File

@ -1,27 +0,0 @@
from operator import itemgetter
class CommKernel:
def __init__(self, dmgr):
super().__init__()
def switch_clock(self, external):
pass
def load(self, kernel_library):
pass
def run(self):
pass
def serve(self, embedding_map, symbolizer, demangler):
pass
def check_system_info(self):
pass
def get_log(self):
return ""
def clear_log(self):
pass

2
artiq/coredevice/comm_mgmt.py
View File

@ -42,7 +42,7 @@ def initialize_connection(host, port):
class CommMgmt:
def __init__(self, dmgr, host, port=1380):
def __init__(self, host, port=1380):
self.host = host
self.port = port

12
artiq/coredevice/core.py
View File

@ -13,6 +13,7 @@ from artiq.compiler.module import Module
from artiq.compiler.embedding import Stitcher
from artiq.compiler.targets import OR1KTarget
from artiq.coredevice.comm_kernel import CommKernel, CommKernelDummy
# Import for side effects (creating the exception classes).
from artiq.coredevice import exceptions
@ -50,6 +51,7 @@ def rtio_get_counter() -> TInt64:
class Core:
"""Core device driver.
:param host: hostname or IP address of the core device.
:param ref_period: period of the reference clock for the RTIO subsystem.
On platforms that use clock multiplication and SERDES-based PHYs,
this is the period after multiplication. For example, with a RTIO core
@ -61,7 +63,6 @@ class Core:
:param ref_multiplier: ratio between the RTIO fine timestamp frequency
and the RTIO coarse timestamp frequency (e.g. SERDES multiplication
factor).
:param comm_device: name of the device used for communications.
"""
kernel_invariants = {
@ -69,13 +70,16 @@ class Core:
"external_clock",
}
def __init__(self, dmgr, ref_period, external_clock=False,
ref_multiplier=8, comm_device="comm"):
def __init__(self, dmgr, host, ref_period, external_clock=False,
ref_multiplier=8):
self.ref_period = ref_period
self.external_clock = external_clock
self.ref_multiplier = ref_multiplier
self.coarse_ref_period = ref_period*ref_multiplier
self.comm = dmgr.get(comm_device)
if host is None:
self.comm = CommKernelDummy()
else:
self.comm = CommKernel(host)
self.first_run = True
self.dmgr = dmgr

2
artiq/dashboard/moninj.py
View File

@ -197,7 +197,7 @@ class _DeviceManager:
try:
if v["type"] == "local":
widget = None
if k == "comm":
if k == "core":
self.core_addr = v["arguments"]["host"]
self.new_core_addr.set()
elif v["module"] == "artiq.coredevice.ttl":

8
artiq/examples/drtio/device_db.py
View File

@ -3,17 +3,11 @@
# The list of devices here is not exhaustive.
device_db = {
"comm": {
"type": "local",
"module": "artiq.coredevice.comm_kernel",
"class": "CommKernel",
"arguments": {"host": "kc705.lab.m-labs.hk"}
},
"core": {
"type": "local",
"module": "artiq.coredevice.core",
"class": "Core",
"arguments": {"ref_period": 2e-9}
"arguments": {"host": "kc705.lab.m-labs.hk", "ref_period": 2e-9}
},
"core_cache": {
"type": "local",

8
artiq/examples/master/device_db.py
View File

@ -3,17 +3,11 @@
# The list of devices here is not exhaustive.
device_db = {
"comm": {
"type": "local",
"module": "artiq.coredevice.comm_kernel",
"class": "CommKernel",
"arguments": {"host": "kc705.lab.m-labs.hk"}
},
"core": {
"type": "local",
"module": "artiq.coredevice.core",
"class": "Core",
"arguments": {"ref_period": 1e-9}
"arguments": {"host": "kc705.lab.m-labs.hk", "ref_period": 1e-9}
},
"core_cache": {
"type": "local",

7
artiq/examples/phaser/device_db.py
View File

@ -1,17 +1,12 @@
# The RTIO channel numbers here are for Phaser on KC705.
device_db = {
"comm": {
"type": "local",
"module": "artiq.coredevice.comm_kernel",
"class": "CommKernel",
"arguments": {"host": "kc705aux.lab.m-labs.hk"}
},
"core": {
"type": "local",
"module": "artiq.coredevice.core",
"class": "Core",
"arguments": {
"host": "kc705aux.lab.m-labs.hk",
"ref_period": 5e-9/6
}
},

2
artiq/frontend/artiq_coreanalyzer.py
View File

@ -43,7 +43,7 @@ def main():
with open(args.read_dump, "rb") as f:
dump = f.read()
else:
core_addr = device_mgr.get_desc("comm")["arguments"]["host"]
core_addr = device_mgr.get_desc("core")["arguments"]["host"]
dump = get_analyzer_dump(core_addr)
decoded_dump = decode_dump(dump)
if args.print_decoded:

2
artiq/frontend/artiq_coreboot.py
View File

@ -36,7 +36,7 @@ def main():
init_logger(args)
device_mgr = DeviceManager(DeviceDB(args.device_db))
try:
core_addr = device_mgr.get_desc("comm")["arguments"]["host"]
core_addr = device_mgr.get_desc("core")["arguments"]["host"]
mgmt = CommMgmt(device_mgr, core_addr)
if args.action == "reboot":
mgmt.reboot()

2
artiq/frontend/artiq_coreconfig.py
View File

@ -52,7 +52,7 @@ def main():
init_logger(args)
device_mgr = DeviceManager(DeviceDB(args.device_db))
try:
comm = device_mgr.get("comm")
comm = device_mgr.get("core").comm
comm.check_system_info()
if args.action == "read":

2
artiq/frontend/artiq_corelog.py
View File

@ -37,7 +37,7 @@ def main():
args = get_argparser().parse_args()
init_logger(args)
core_addr = DeviceDB(args.device_db).get("comm")["arguments"]["host"]
core_addr = DeviceDB(args.device_db).get("core")["arguments"]["host"]
mgmt = CommMgmt(None, core_addr)
try:
if args.action == "set_level":

4
artiq/test/coredevice/test_analyzer.py
View File

@ -40,7 +40,7 @@ class WriteLog(EnvExperiment):
class AnalyzerTest(ExperimentCase):
def test_ttl_pulse(self):
core_host = self.device_mgr.get_desc("comm")["arguments"]["host"]
core_host = self.device_mgr.get_desc("core")["arguments"]["host"]
exp = self.create(CreateTTLPulse)
exp.initialize_io()
@ -64,7 +64,7 @@ class AnalyzerTest(ExperimentCase):
1000, delta=1)
def test_rtio_log(self):
core_host = self.device_mgr.get_desc("comm")["arguments"]["host"]
core_host = self.device_mgr.get_desc("core")["arguments"]["host"]
exp = self.create(WriteLog)
get_analyzer_dump(core_host) # clear analyzer buffer

2
artiq/test/coredevice/test_moninj.py
View File

@ -6,7 +6,7 @@ from artiq.test.hardware_testbench import ExperimentCase
class MonInjTest(ExperimentCase):
def test_moninj(self):
core_host = self.device_mgr.get_desc("comm")["arguments"]["host"]
core_host = self.device_mgr.get_desc("core")["arguments"]["host"]
loop_out_channel = self.device_mgr.get_desc("loop_out")["arguments"]["channel"]
loop_in_channel = self.device_mgr.get_desc("loop_in")["arguments"]["channel"]

6
artiq/test/coredevice/test_rtio.py
View File

@ -402,7 +402,7 @@ class CoredeviceTest(ExperimentCase):
self.execute(SequenceError)
def test_collision(self):
core_addr = self.device_mgr.get_desc("comm")["arguments"]["host"]
core_addr = self.device_mgr.get_desc("core")["arguments"]["host"]
mgmt = CommMgmt(self.device_mgr, core_addr)
mgmt.clear_log()
self.execute(Collision)
@ -411,7 +411,7 @@ class CoredeviceTest(ExperimentCase):
mgmt.close()
def test_address_collision(self):
core_addr = self.device_mgr.get_desc("comm")["arguments"]["host"]
core_addr = self.device_mgr.get_desc("core")["arguments"]["host"]
mgmt = CommMgmt(self.device_mgr, core_addr)
mgmt.clear_log()
self.execute(AddressCollision)
@ -576,7 +576,7 @@ class DMATest(ExperimentCase):
exp.nested()
def test_dma_trace(self):
core_host = self.device_mgr.get_desc("comm")["arguments"]["host"]
core_host = self.device_mgr.get_desc("core")["arguments"]["host"]
exp = self.create(_DMA)
exp.record()

8
artiq/test/lit/devirtualization/device_db.py
View File

@ -1,14 +1,8 @@
device_db = {
"comm": {
"type": "local",
"module": "artiq.coredevice.comm_kernel_dummy",
"class": "CommKernel",
"arguments": {}
},
"core": {
"type": "local",
"module": "artiq.coredevice.core",
"class": "Core",
"arguments": {"ref_period": 1e-9}
"arguments": {"host": None, "ref_period": 1e-9}
}
}

8
artiq/test/lit/embedding/device_db.py
View File

@ -1,14 +1,8 @@
device_db = {
"comm": {
"type": "local",
"module": "artiq.coredevice.comm_kernel_dummy",
"class": "CommKernel",
"arguments": {}
},
"core": {
"type": "local",
"module": "artiq.coredevice.core",
"class": "Core",
"arguments": {"ref_period": 1e-9}
"arguments": {"host": None, "ref_period": 1e-9}
}
}

8
artiq/test/lit/escape/device_db.py
View File

@ -1,14 +1,8 @@
device_db = {
"comm": {
"type": "local",
"module": "artiq.coredevice.comm_kernel_dummy",
"class": "CommKernel",
"arguments": {}
},
"core": {
"type": "local",
"module": "artiq.coredevice.core",
"class": "Core",
"arguments": {"ref_period": 1e-9}
"arguments": {"host": None, "ref_period": 1e-9}
}
}

8
artiq/test/lit/regression/device_db.py
View File

@ -1,14 +1,8 @@
device_db = {
"comm": {
"type": "local",
"module": "artiq.coredevice.comm_kernel_dummy",
"class": "CommKernel",
"arguments": {}
},
"core": {
"type": "local",
"module": "artiq.coredevice.core",
"class": "Core",
"arguments": {"ref_period": 1e-9}
"arguments": {"host": None, "ref_period": 1e-9}
}
}