From 5c6e3949280c81b65b7b709bcbdbc3f70a192448 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Mon, 30 Dec 2019 22:17:44 +0800
Subject: [PATCH] ddmtd: add collector

---
 artiq/gateware/drtio/wrpll/core.py  | 21 ++++++++++++++++++++-
 artiq/gateware/drtio/wrpll/ddmtd.py | 20 ++++++++++++++++++++
 2 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/artiq/gateware/drtio/wrpll/core.py b/artiq/gateware/drtio/wrpll/core.py
index a37aa1a4b..dc026f3b9 100644
--- a/artiq/gateware/drtio/wrpll/core.py
+++ b/artiq/gateware/drtio/wrpll/core.py
@@ -4,7 +4,7 @@ from migen.genlib.cdc import MultiReg, PulseSynchronizer
 from misoc.interconnect.csr import *
 
 from artiq.gateware.drtio.wrpll.si549 import Si549
-from artiq.gateware.drtio.wrpll.ddmtd import DDMTD
+from artiq.gateware.drtio.wrpll.ddmtd import DDMTD, Collector
 from artiq.gateware.drtio.wrpll import thls, filters
 
 
@@ -72,8 +72,27 @@ class WRPLL(Module, AutoCSR):
         self.submodules.ddmtd_main = DDMTD(ddmtd_counter, ddmtd_inputs.main_xo)
 
         helper_cd = ClockDomainsRenamer("helper")
+        self.submodules.collector = helper_cd(Collector(N))
         self.submodules.filter_helper = helper_cd(thls.make(filters.helper, data_width=48))
         self.submodules.filter_main = helper_cd(thls.make(filters.main, data_width=48))
+
+        self.comb += [
+            self.collector.tag_helper.eq(self.ddmtd_helper.h_tag),
+            self.collector.tag_helper_update.eq(self.ddmtd_helper.h_tag_update),
+            self.collector.tag_main.eq(self.ddmtd_main.h_tag),
+            self.collector.tag_main_update.eq(self.ddmtd_main.h_tag_update)
+        ]
+
+        # compensate the 1 cycle latency of the collector
+        self.sync.helper += [
+            self.filter_helper.input.eq(self.ddmtd_helper.h_tag),
+            self.filter_helper.input_stb.eq(self.ddmtd_helper.h_tag_update)
+        ]
+        self.comb += [
+            self.filter_main.input.eq(self.collector.output),
+            self.filter_main.input_stb.eq(self.collector.output_update)
+        ]
+
         self.comb += [
             self.helper_dcxo.adpll_stb.eq(self.filter_helper.output_stb),
             self.helper_dcxo.adpll.eq(self.filter_helper.output),
diff --git a/artiq/gateware/drtio/wrpll/ddmtd.py b/artiq/gateware/drtio/wrpll/ddmtd.py
index f46df4463..2fe7f7e64 100644
--- a/artiq/gateware/drtio/wrpll/ddmtd.py
+++ b/artiq/gateware/drtio/wrpll/ddmtd.py
@@ -103,3 +103,23 @@ class DDMTD(Module, AutoCSR):
                 self.arm.w.eq(0),
             )
         ]
+
+
+class Collector(Module):
+    def __init__(self, N):
+        self.tag_helper = Signal(N)
+        self.tag_helper_update = Signal()
+        self.tag_main = Signal(N)
+        self.tag_main_update = Signal()
+
+        self.output = Signal(N)
+        self.output_update = Signal(N)
+
+        # # #
+
+        last_tag_main = Signal(N)
+        self.sync += [
+            If(self.tag_main_update, last_tag_main.eq(self.tag_main)),
+            self.output_update.eq(self.tag_helper_update),
+            self.output.eq(last_tag_main - self.tag_helper)
+        ]