M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

wrpll/thls: fix opcode decoding

This commit is contained in:
Sebastien Bourdeauducq 2019-08-15 17:12:48 +08:00
parent 19620948bf
commit 5c3974c265
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
artiq/gateware/wrpll/thls.py
View File

@ -530,6 +530,7 @@ class ProcessorImpl(Module):
self.submodules += units self.submodules += units
for unit in units: for unit in units:
self.sync += unit.stb_i.eq(0)
self.comb += [ self.comb += [
unit.i0.eq(data_read_port0.dat_r), unit.i0.eq(data_read_port0.dat_r),
unit.i1.eq(data_read_port1.dat_r), unit.i1.eq(data_read_port1.dat_r),
@ -552,7 +553,7 @@ class ProcessorImpl(Module):
(OutputIsn.opcode, outu) (OutputIsn.opcode, outu)
] ]
for allocated_opcode, unit in decode_table: for allocated_opcode, unit in decode_table:
self.sync += unit.stb_i.eq(pc_en & (opcode == allocated_opcode)) self.sync += If(pc_en & (opcode == allocated_opcode), unit.stb_i.eq(1))
fsm = FSM() fsm = FSM()
self.submodules += fsm self.submodules += fsm