From 5b5db1433b148d2176617776e8c8cb5f40c347d1 Mon Sep 17 00:00:00 2001 From: pca006132 Date: Mon, 11 Jan 2021 19:43:12 +0800 Subject: [PATCH] Revert "compiler: enabled vectorize option" This reverts commit 636898c3021ec89bd1b0bb91fa28e6c12fdf2725. --- RELEASE_NOTES.rst | 1 - artiq/compiler/targets.py | 4 ---- 2 files changed, 5 deletions(-) diff --git a/RELEASE_NOTES.rst b/RELEASE_NOTES.rst index 8b17bac8c..4ab9f0537 100644 --- a/RELEASE_NOTES.rst +++ b/RELEASE_NOTES.rst @@ -28,7 +28,6 @@ Highlights: - SERDES TTL inputs can now detect edges on pulses that are shorter than the RTIO period (https://github.com/m-labs/artiq/issues/1432) - Improved performance for kernel RPC involving list and array. - - Improved performance for computation involving loops. * Coredevice SI to mu conversions now always return valid codes, or raise a ``ValueError``. * Zotino now exposes ``voltage_to_mu()`` * ``ad9910``: The maximum amplitude scale factor is now ``0x3fff`` (was ``0x3ffe`` diff --git a/artiq/compiler/targets.py b/artiq/compiler/targets.py index 8a9be0efc..9ebc7907d 100644 --- a/artiq/compiler/targets.py +++ b/artiq/compiler/targets.py @@ -105,11 +105,7 @@ class Target: return llmachine def optimize(self, llmodule): - pmb = llvm.create_pass_manager_builder() - pmb.slp_vectorize = True - pmb.loop_vectorize = True llpassmgr = llvm.create_module_pass_manager() - pmb.populate(llpassmgr) # Register our alias analysis passes. llpassmgr.add_basic_alias_analysis_pass()