From 5b50f5fe05b63bc3bb2ea8a33d015c1ce628a462 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 27 Jul 2015 10:50:50 +0800 Subject: [PATCH] rtio/ttl_serdes_7series: use recommended OSERDES T configuration --- artiq/gateware/rtio/phy/ttl_serdes_7series.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/artiq/gateware/rtio/phy/ttl_serdes_7series.py b/artiq/gateware/rtio/phy/ttl_serdes_7series.py index ccb32ab5e..b2322b4f5 100644 --- a/artiq/gateware/rtio/phy/ttl_serdes_7series.py +++ b/artiq/gateware/rtio/phy/ttl_serdes_7series.py @@ -12,9 +12,9 @@ class _OSERDESE2_8X(Module): # # # o = self.o - self.specials += Instance("OSERDESE2", p_DATA_RATE_OQ="DDR", - p_DATA_RATE_TQ="DDR", p_DATA_WIDTH=8, - p_TRISTATE_WIDTH=1, + self.specials += Instance("OSERDESE2", + p_DATA_RATE_OQ="DDR", p_DATA_RATE_TQ="BUF", + p_DATA_WIDTH=8, p_TRISTATE_WIDTH=1, o_OQ=pad, o_TQ=self.t_out, i_CLK=ClockSignal("rtiox4"), i_CLKDIV=ClockSignal("rio_phy"),