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drtio/transceiver/gth: fix single transceiver case

This commit is contained in:
Florent Kermarrec 2018-02-23 12:15:47 +01:00
parent cff85ee13b
commit 5b0f9cc6fd
1 changed files with 1 additions and 1 deletions
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artiq/gateware/drtio/transceiver/gth_ultrascale.py
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@ -205,7 +205,7 @@ class GTHSingle(Module):
tx_reset_deglitched.attr.add("no_retiming") tx_reset_deglitched.attr.add("no_retiming")
self.sync += tx_reset_deglitched.eq(~tx_init.done) self.sync += tx_reset_deglitched.eq(~tx_init.done)
self.clock_domains.cd_rtio_tx = ClockDomain() self.clock_domains.cd_rtio_tx = ClockDomain()
if mode == "master": if mode == "master" or mode == "single":
self.specials += \ self.specials += \
Instance("BUFG_GT", i_I=self.txoutclk, o_O=self.cd_rtio_tx.clk, i_DIV=0) Instance("BUFG_GT", i_I=self.txoutclk, o_O=self.cd_rtio_tx.clk, i_DIV=0)
self.specials += AsyncResetSynchronizer(self.cd_rtio_tx, tx_reset_deglitched) self.specials += AsyncResetSynchronizer(self.cd_rtio_tx, tx_reset_deglitched)