From 5af4609053d210f81ee09ae798f94153aa8d1978 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 9 Mar 2018 19:06:47 +0100
Subject: [PATCH] libboard/sdram: limit write leveling scan to "512 - initial
 dqs taps delay" on ultrascale

---
 artiq/firmware/libboard/sdram.rs | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/artiq/firmware/libboard/sdram.rs b/artiq/firmware/libboard/sdram.rs
index a42e5c668..aa8b0330b 100644
--- a/artiq/firmware/libboard/sdram.rs
+++ b/artiq/firmware/libboard/sdram.rs
@@ -39,6 +39,11 @@ mod ddr {
         enable_write_leveling(true);
         spin_cycles(100);
 
+        let mut ddrphy_max_delay : u16 = DDRPHY_MAX_DELAY;
+        #[cfg(kusddrphy)] {
+            ddrphy_max_delay -= ddrphy::wdly_dqs_taps_read();
+        }
+
         for n in 0..DQS_SIGNAL_COUNT {
             let dq_addr = dfii::PI0_RDDATA_ADDR
                                .offset((DQS_SIGNAL_COUNT - 1 - n) as isize);
@@ -55,7 +60,7 @@ mod ddr {
             }
 
             let mut dq;
-            for _ in 0..DDRPHY_MAX_DELAY {
+            for _ in 0..ddrphy_max_delay {
                 ddrphy::wlevel_strobe_write(1);
                 spin_cycles(10);
                 dq = ptr::read_volatile(dq_addr);
@@ -87,6 +92,11 @@ mod ddr {
         enable_write_leveling(true);
         spin_cycles(100);
 
+        let mut ddrphy_max_delay : u16 = DDRPHY_MAX_DELAY;
+        #[cfg(kusddrphy)] {
+            ddrphy_max_delay -= ddrphy::wdly_dqs_taps_read();
+        }
+        
         let mut failed = false;
         for n in 0..DQS_SIGNAL_COUNT {
             let dq_addr = dfii::PI0_RDDATA_ADDR
@@ -108,7 +118,7 @@ mod ddr {
 
             let mut incr_delay = || {
                 delay[n] += 1;
-                if delay[n] >= DDRPHY_MAX_DELAY {
+                if delay[n] >= ddrphy_max_delay {
                     failed = true;
                     return false
                 }