From 59e8b77fca0ff4e4f5f22a5a04379528f098effe Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Fri, 20 Dec 2019 18:58:50 +0800
Subject: [PATCH] coredevice/shiftreg: add get method

---
 artiq/coredevice/shiftreg.py | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/artiq/coredevice/shiftreg.py b/artiq/coredevice/shiftreg.py
index a71d6e217..cf7b9466c 100644
--- a/artiq/coredevice/shiftreg.py
+++ b/artiq/coredevice/shiftreg.py
@@ -6,13 +6,15 @@ class ShiftReg:
     """Driver for shift registers/latch combos connected to TTLs"""
     kernel_invariants = {"dt", "n"}
     
-    def __init__(self, dmgr, clk, ser, latch, n=32, dt=10*us):
+    def __init__(self, dmgr, clk, ser, latch, n=32, dt=10*us, ser_in=None):
         self.core = dmgr.get("core")
         self.clk = dmgr.get(clk)
         self.ser = dmgr.get(ser)
         self.latch = dmgr.get(latch)
         self.n = n
         self.dt = dt
+        if ser_in is not None:
+            self.ser_in = dmgr.get(ser_in)
 
     @kernel
     def set(self, data):
@@ -34,3 +36,18 @@ class ShiftReg:
         delay(self.dt)
         self.latch.off()
         delay(self.dt)
+
+    @kernel
+    def get(self):
+        delay(-2*(self.n + 1)*self.dt)
+        data = 0
+        for i in range(self.n):
+            data <<= 1
+            if self.ser_in.sample_input():
+                data |= 1
+            delay(self.dt)
+            self.clk.on()
+            delay(self.dt)
+            self.clk.off()
+        delay(self.dt)
+        return data