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https://github.com/m-labs/artiq.git
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commit
5985595845
@ -3,6 +3,14 @@
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Release notes
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=============
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Unreleased
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----------
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Highlights:
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* Implemented Phaser-servo. This requires recent gateware on Phaser.
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ARTIQ-7
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-------
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@ -40,6 +40,14 @@ PHASER_ADDR_DUC1_P = 0x26
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PHASER_ADDR_DAC1_DATA = 0x28
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PHASER_ADDR_DAC1_TEST = 0x2c
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# servo registers
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PHASER_ADDR_SERVO_CFG0 = 0x30
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PHASER_ADDR_SERVO_CFG1 = 0x31
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# 0x32 - 0x71 servo coefficients + offset data
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PHASER_ADDR_SERVO_DATA_BASE = 0x32
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PHASER_SEL_DAC = 1 << 0
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PHASER_SEL_TRF0 = 1 << 1
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PHASER_SEL_TRF1 = 1 << 2
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@ -58,6 +66,11 @@ PHASER_DAC_SEL_TEST = 1
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PHASER_HW_REV_VARIANT = 1 << 4
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SERVO_COEFF_WIDTH = 16
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SERVO_DATA_WIDTH = 16
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SERVO_COEFF_SHIFT = 14
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SERVO_T_CYCLE = (32+12+192+24+4)*ns # Must match gateware ADC parameters
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class Phaser:
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"""Phaser 4-channel, 16-bit, 1 GS/s DAC coredevice driver.
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@ -112,6 +125,31 @@ class Phaser:
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configured through a shared SPI bus that is accessed and controlled via
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FPGA registers.
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Each phaser output channel features a servo to control the RF output amplitude
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using feedback from an ADC. The servo consists of a first order IIR (infinite
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impulse response) filter fed by the ADC and a multiplier that scales the I
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and Q datastreams from the DUC by the IIR output. The IIR state is updated at
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the 3.788 MHz ADC sampling rate.
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Each channel IIR features 4 profiles, each consisting of the [b0, b1, a1] filter
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coefficients as well as an output offset. The coefficients and offset can be
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set for each profile individually and the profiles each have their own ``y0``,
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``y1`` output registers (the ``x0``, ``x1`` inputs are shared). To avoid
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transient effects, care should be taken to not update the coefficents in the
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currently selected profile.
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The servo can be en- or disabled for each channel. When disabled, the servo
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output multiplier is simply bypassed and the datastream reaches the DAC unscaled.
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The IIR output can be put on hold for each channel. In hold mode, the filter
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still ingests samples and updates its input ``x0`` and ``x1`` registers, but
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does not update the ``y0``, ``y1`` output registers.
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After power-up the servo is disabled, in profile 0, with coefficients [0, 0, 0]
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and hold is enabled. If older gateware without ther servo is loaded onto the
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Phaser FPGA, the device simply behaves as if the servo is disabled and none of
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the servo functions have any effect.
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.. note:: Various register settings of the DAC and the quadrature
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upconverters are available to be modified through the `dac`, `trf0`,
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`trf1` dictionaries. These can be set through the device database
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@ -310,6 +348,8 @@ class Phaser:
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delay(.1*ms)
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channel.set_att_mu(0x00) # minimum attenuation
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channel.set_servo(profile=0, enable=0, hold=1)
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# test oscillators and DUC
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for i in range(len(channel.oscillator)):
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oscillator = channel.oscillator[i]
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@ -382,6 +422,12 @@ class Phaser:
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response = rtio_input_data(self.channel_base)
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return response >> self.miso_delay
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@kernel
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def write16(self, addr, data: TInt32):
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"""Write 16 bit to a sequence of FPGA registers."""
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self.write8(addr, data >> 8)
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self.write8(addr + 1, data)
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@kernel
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def write32(self, addr, data: TInt32):
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"""Write 32 bit to a sequence of FPGA registers."""
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@ -1039,6 +1085,133 @@ class PhaserChannel:
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data = data ^ ((1 << 12) | (1 << 13))
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self.trf_write(data)
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@kernel
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def set_servo(self, profile=0, enable=0, hold=0):
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"""Set the servo configuration.
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:param enable: 1 to enable servo, 0 to disable servo (default). If disabled,
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the servo is bypassed and hold is enforced since the control loop is broken.
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:param hold: 1 to hold the servo IIR filter output constant, 0 for normal operation.
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:param profile: Profile index to select for channel. (0 to 3)
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"""
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if (profile < 0) or (profile > 3):
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raise ValueError("invalid profile index")
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addr = PHASER_ADDR_SERVO_CFG0 + self.index
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# enforce hold if the servo is disabled
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data = (profile << 2) | (((hold | ~enable) & 1) << 1) | (enable & 1)
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self.phaser.write8(addr, data)
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@kernel
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def set_iir_mu(self, profile, b0, b1, a1, offset):
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"""Load a servo profile consiting of the three filter coefficients and an output offset.
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Avoid setting the IIR parameters of the currently active profile.
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The recurrence relation is (all data signed and MSB aligned):
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.. math::
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a_0 y_n = a_1 y_{n - 1} + b_0 x_n + b_1 x_{n - 1} + o
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Where:
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* :math:`y_n` and :math:`y_{n-1}` are the current and previous
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filter outputs, clipped to :math:`[0, 1[`.
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* :math:`x_n` and :math:`x_{n-1}` are the current and previous
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filter inputs in :math:`[-1, 1[`.
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* :math:`o` is the offset
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* :math:`a_0` is the normalization factor :math:`2^{14}`
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* :math:`a_1` is the feedback gain
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* :math:`b_0` and :math:`b_1` are the feedforward gains for the two
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delays
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.. seealso:: :meth:`set_iir`
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:param profile: Profile to set (0 to 3)
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:param b0: b0 filter coefficient (16 bit signed)
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:param b1: b1 filter coefficient (16 bit signed)
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:param a1: a1 filter coefficient (16 bit signed)
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:param offset: Output offset (16 bit signed)
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"""
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if (profile < 0) or (profile > 3):
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raise ValueError("invalid profile index")
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# 32 byte-sized data registers per channel and 8 (2 bytes * (3 coefficients + 1 offset)) registers per profile
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addr = PHASER_ADDR_SERVO_DATA_BASE + (8 * profile) + (self.index * 32)
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for data in [b0, b1, a1, offset]:
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self.phaser.write16(addr, data)
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addr += 2
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@kernel
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def set_iir(self, profile, kp, ki=0., g=0., x_offset=0., y_offset=0.):
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"""Set servo profile IIR coefficients.
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Avoid setting the IIR parameters of the currently active profile.
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Gains are given in units of output full per scale per input full scale.
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.. note:: Due to inherent constraints of the fixed point datatypes and IIR
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filters, the ``x_offset`` (setpoint) resolution depends on the selected gains.
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Low ``ki`` gains will lead to a low ``x_offset`` resolution.
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The transfer function is (up to time discretization and
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coefficient quantization errors):
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.. math::
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H(s) = k_p + \\frac{k_i}{s + \\frac{k_i}{g}}
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Where:
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* :math:`s = \\sigma + i\\omega` is the complex frequency
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* :math:`k_p` is the proportional gain
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* :math:`k_i` is the integrator gain
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* :math:`g` is the integrator gain limit
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:param profile: Profile number (0-3)
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:param kp: Proportional gain. This is usually negative (closed
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loop, positive ADC voltage, positive setpoint). When 0, this
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implements a pure I controller.
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:param ki: Integrator gain (rad/s). Equivalent to the gain at 1 Hz.
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When 0 (the default) this implements a pure P controller.
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Same sign as ``kp``.
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:param g: Integrator gain limit (1). When 0 (the default) the
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integrator gain limit is infinite. Same sign as ``ki``.
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:param x_offset: IIR input offset. Used as the negative
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setpoint when stabilizing to a desired input setpoint. Will
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be converted to an equivalent output offset and added to y_offset.
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:param y_offset: IIR output offset.
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"""
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NORM = 1 << SERVO_COEFF_SHIFT
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COEFF_MAX = 1 << SERVO_COEFF_WIDTH - 1
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DATA_MAX = 1 << SERVO_DATA_WIDTH - 1
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kp *= NORM
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if ki == 0.:
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# pure P
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a1 = 0
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b1 = 0
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b0 = int(round(kp))
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else:
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# I or PI
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ki *= NORM*SERVO_T_CYCLE/2.
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if g == 0.:
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c = 1.
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a1 = NORM
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else:
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c = 1./(1. + ki/(g*NORM))
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a1 = int(round((2.*c - 1.)*NORM))
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b0 = int(round(kp + ki*c))
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b1 = int(round(kp + (ki - 2.*kp)*c))
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if b1 == -b0:
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raise ValueError("low integrator gain and/or gain limit")
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if (b0 >= COEFF_MAX or b0 < -COEFF_MAX or
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b1 >= COEFF_MAX or b1 < -COEFF_MAX):
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raise ValueError("high gains")
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forward_gain = (b0 + b1) * (1 << SERVO_DATA_WIDTH - 1 - SERVO_COEFF_SHIFT)
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effective_offset = int(round(DATA_MAX * y_offset + forward_gain * x_offset))
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self.set_iir_mu(profile, b0, b1, a1, effective_offset)
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class PhaserOscillator:
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"""Phaser IQ channel oscillator (NCO/DDS).
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