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artiq
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pipistrello: add rtio.Analyzer()

This commit is contained in:
Robert Jördens 2016-01-18 19:17:44 -07:00
parent 063e88d75a
commit 57ce78c54d
1 changed files with 5 additions and 1 deletions
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6
artiq/gateware/targets/pipistrello.py
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@ -106,7 +106,8 @@ class NIST_QC1(BaseSoC, AMPSoC):
"rtio": None, # mapped on Wishbone instead
"rtio_crg": 10,
"kernel_cpu": 11,
"rtio_moninj": 12
"rtio_moninj": 12,
"rtio_analyzer": 13
}
csr_map.update(BaseSoC.csr_map)
mem_map = {
@ -208,6 +209,9 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
self.add_csr_region("rtio", self.mem_map["rtio"] | 0x80000000, 32,
rtio_csrs)
self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio,
self.get_native_sdram_if())
def main():
parser = argparse.ArgumentParser(