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add servo docu
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@ -122,6 +122,26 @@ class Phaser:
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configured through a shared SPI bus that is accessed and controlled via
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FPGA registers.
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Each phaser output channel features a servo to control the RF output amplitude
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using feedback from an ADC. The servo consists of a first order IIR (infinite
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impulse response) filter fed by the ADC and a multiplier that scales the I
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and Q datastreams from the DUC by the IIR output.
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Each channels IIR features 4 profiles, each consisting of the [b0, b1, a1] filter
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coefficients as well as an output offset. The coefficients and offset can be
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set for each profile individually and the profiles each have their own filter
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state. To avoid transient effects, care should be taken to not update the
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coefficents in the currently selected profile.
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The IIR output can be put on hold for each channel. In hold mode, the filter
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still ingests samples and updates its input x0 and x1 registers, but does not
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update the y0, y1 output registers. The servo can also be bypassed.
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After power-up the servo is bypassed, in profile 0, with coefficients [0, 0, 0]
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and hold is disabled. If older gateware without ther servo is loaded onto the
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Phaser FPGA, the device simply behaves as if the servo is bypassed and none of
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the servo functions have any effect.
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.. note:: Various register settings of the DAC and the quadrature
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upconverters are available to be modified through the `dac`, `trf0`,
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`trf1` dictionaries. These can be set through the device database
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