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mirny: fix doc formatting

This commit is contained in:
Florian Agbuya 2023-09-05 11:38:49 +08:00 committed by Sébastien Bourdeauducq
parent f6ce6bb806
commit 568ef2336c
1 changed files with 5 additions and 2 deletions
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7
artiq/coredevice/mirny.py
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@ -183,7 +183,7 @@ class Almazny:
"""
Almazny (High frequency mezzanine board for Mirny)
:param host_mirny - Mirny device Almazny is connected to
:param host_mirny: Mirny device Almazny is connected to
"""
def __init__(self, dmgr, host_mirny):
@ -223,8 +223,9 @@ class Almazny:
def set_att(self, channel, att, rf_switch=True):
"""
Sets attenuators on chosen shift register (channel).
:param channel - index of the register [0-3]
:param att_mu - attenuation setting in dBm [0-31.5]
:param att - attenuation setting in dBm [0-31.5]
:param rf_switch - rf switch (bool)
"""
self.set_att_mu(channel, self.att_to_mu(att), rf_switch)
@ -233,6 +234,7 @@ class Almazny:
def set_att_mu(self, channel, att_mu, rf_switch=True):
"""
Sets attenuators on chosen shift register (channel).
:param channel - index of the register [0-3]
:param att_mu - attenuation setting in machine units [0-63]
:param rf_switch - rf switch (bool)
@ -245,6 +247,7 @@ class Almazny:
def output_toggle(self, oe):
"""
Toggles output on all shift registers on or off.
:param oe - toggle output enable (bool)
"""
self.output_enable = oe