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eem: finalize grabber support

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This commit is contained in:
Sebastien Bourdeauducq 2018-05-28 22:43:06 +08:00
parent 2612fd1e72
commit 563e434e15
1 changed files with 32 additions and 32 deletions
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64
artiq/gateware/eem.py
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@ -3,7 +3,7 @@ from migen.build.generic_platform import *
from migen.genlib.io import DifferentialOutput
from artiq.gateware import rtio
from artiq.gateware.rtio.phy import spi2
from artiq.gateware.rtio.phy import spi2, grabber
def _eem_signal(i):
@ -354,16 +354,10 @@ class Grabber(_EEM):
def io(eem, eem_aux):
ios = [
("grabber{}_video".format(eem), 0,
Subsignal("xclk_p", Pins(_eem_pin(eem, 0, "p"))),
Subsignal("xclk_n", Pins(_eem_pin(eem, 0, "n"))),
Subsignal("x0_p", Pins(_eem_pin(eem, 1, "p"))),
Subsignal("x0_n", Pins(_eem_pin(eem, 1, "n"))),
Subsignal("x1_p", Pins(_eem_pin(eem, 2, "p"))),
Subsignal("x1_n", Pins(_eem_pin(eem, 2, "n"))),
Subsignal("x2_p", Pins(_eem_pin(eem, 3, "p"))),
Subsignal("x2_n", Pins(_eem_pin(eem, 3, "n"))),
Subsignal("x3_p", Pins(_eem_pin(eem, 4, "p"))),
Subsignal("x3_n", Pins(_eem_pin(eem, 4, "n"))),
Subsignal("clk_p", Pins(_eem_pin(eem, 0, "p"))),
Subsignal("clk_n", Pins(_eem_pin(eem, 0, "n"))),
Subsignal("sdi_p", Pins(*[_eem_pin(eem, i, "p") for i in range(1, 5)])),
Subsignal("sdi_n", Pins(*[_eem_pin(eem, i, "n") for i in range(1, 5)])),
IOStandard("LVDS_25")
),
("grabber{}_cc0".format(eem), 0,
@ -385,16 +379,10 @@ class Grabber(_EEM):
if eem_aux is not None:
ios += [
("grabber{}_video_m".format(eem), 0,
Subsignal("yclk_p", Pins(_eem_pin(eem_aux, 0, "p"))),
Subsignal("yclk_n", Pins(_eem_pin(eem_aux, 0, "n"))),
Subsignal("y0_p", Pins(_eem_pin(eem_aux, 1, "p"))),
Subsignal("y0_n", Pins(_eem_pin(eem_aux, 1, "n"))),
Subsignal("y1_p", Pins(_eem_pin(eem_aux, 2, "p"))),
Subsignal("y1_n", Pins(_eem_pin(eem_aux, 2, "n"))),
Subsignal("y2_p", Pins(_eem_pin(eem_aux, 3, "p"))),
Subsignal("y2_n", Pins(_eem_pin(eem_aux, 3, "n"))),
Subsignal("y3_p", Pins(_eem_pin(eem_aux, 4, "p"))),
Subsignal("y3_n", Pins(_eem_pin(eem_aux, 4, "n"))),
Subsignal("clk_p", Pins(_eem_pin(eem_aux, 0, "p"))),
Subsignal("clk_n", Pins(_eem_pin(eem_aux, 0, "n"))),
Subsignal("sdi_p", Pins(*[_eem_pin(eem_aux, i, "p") for i in range(1, 5)])),
Subsignal("sdi_n", Pins(*[_eem_pin(eem_aux, i, "n") for i in range(1, 5)])),
IOStandard("LVDS_25")
),
("grabber{}_serrx".format(eem), 0,
@ -416,16 +404,28 @@ class Grabber(_EEM):
return ios
@classmethod
def add_std(cls, target, eem, eem_aux, ttl_out_cls):
def add_std(cls, target, eem, eem_aux=None, ttl_out_cls=None):
cls.add_extension(target, eem, eem_aux)
for signal in "cc0 cc1 cc2".split():
pads = target.platform.request("grabber{}_{}".format(eem, signal))
phy = ttl_out_cls(pads.p, pads.n)
target.submodules += phy
target.rtio_channels.append(rtio.Channel.from_phy(phy))
if eem_aux is not None:
pads = target.platform.request("grabber{}_cc3".format(eem))
phy = ttl_out_cls(pads.p, pads.n)
target.submodules += phy
target.rtio_channels.append(rtio.Channel.from_phy(phy))
phy = grabber.Grabber(target.platform.request(
"grabber{}_video".format(eem)))
name = "grabber{}".format(len(target.grabber_csr_group))
setattr(target.submodules, name, phy)
target.grabber_csr_group.append(name)
target.csr_devices.append(name)
target.rtio_channels += [
rtio.Channel(phy.config),
rtio.Channel(phy.gate_data)
]
if ttl_out_cls is not None:
for signal in "cc0 cc1 cc2".split():
pads = target.platform.request("grabber{}_{}".format(eem, signal))
phy = ttl_out_cls(pads.p, pads.n)
target.submodules += phy
target.rtio_channels.append(rtio.Channel.from_phy(phy))
if eem_aux is not None:
pads = target.platform.request("grabber{}_cc3".format(eem))
phy = ttl_out_cls(pads.p, pads.n)
target.submodules += phy
target.rtio_channels.append(rtio.Channel.from_phy(phy))