coredevice,runtime: put ref_period into the ddb

artiq/coredevice/comm_generic.py

@@ -108,12 +108,7 @@ class CommGeneric:
         if runtime_id != "AROR":
             raise UnsupportedDevice("Unsupported runtime ID: {}"
                                     .format(runtime_id))
-        ref_freq_i, ref_freq_fn, ref_freq_fd = struct.unpack(
+        return Environment()
-            ">lBB", self._read(6))
-        ref_freq = (ref_freq_i + Fraction(ref_freq_fn, ref_freq_fd))*units.Hz
-        ref_period = 1/ref_freq
-        logger.debug("environment ref_period: %s", ref_period)
-        return Environment(ref_period)
 
     def switch_clock(self, external):
         self._write(struct.pack(
@@ -140,8 +135,6 @@ class CommGeneric:
             self._write(struct.pack(">B", ord(c)))
         logger.debug("running kernel: %s", kname)
 
-
-
     def _receive_rpc_values(self):
         r = []
         while True:

artiq/coredevice/core.py

@@ -47,19 +47,15 @@ def _no_debug_unparse(label, node):
 class Core(AutoDB):
     class DBKeys:
         comm = Device()
-        external_clock = Parameter(None)
+        ref_period = Argument()
+        external_clock = Argument(False)
 
     def build(self):
         self.runtime_env = self.comm.get_runtime_env()
         self.core = self
         self.comm.core = self
         
-        if self.external_clock is None:
+        self.comm.switch_clock(self.external_clock)
-            self.ref_period = self.runtime_env.internal_ref_period
-            self.comm.switch_clock(False)
-        else:
-            self.ref_period = 1/self.external_clock
-            self.comm.switch_clock(True)
         self.initial_time = int64(self.runtime_env.warmup_time/self.ref_period)
 
     def transform_stack(self, func_def, rpc_map, exception_map,

artiq/coredevice/runtime.py

@@ -190,9 +190,8 @@ def _debug_dump_obj(obj):
 
 
 class Environment(LinkInterface):
-    def __init__(self, internal_ref_period):
+    def __init__(self):
         self.cpu_type = "or1k"
-        self.internal_ref_period = internal_ref_period
         # allow 1ms for all initial DDS programming
         self.warmup_time = 1*units.ms
 
@@ -203,5 +202,4 @@ class Environment(LinkInterface):
         return obj
 
     def __repr__(self):
-        return "<Environment {} {}>".format(self.cpu_type,
+        return "<Environment {}>".format(self.cpu_type)
-                                            str(1/self.ref_period))

artiq/gateware/rtio/core.py

@@ -1,5 +1,3 @@
-from fractions import Fraction
-
 from migen.fhdl.std import *
 from migen.bank.description import *
 from migen.genlib.misc import optree
@@ -255,13 +253,6 @@ class Channel:
         self.ififo_depth = ififo_depth
 
 
-class _CSRs(AutoCSR):
-    def __init__(self):
-        self.frequency_i = CSRStatus(32)
-        self.frequency_fn = CSRStatus(8)
-        self.frequency_fd = CSRStatus(8)
-
-
 class _KernelCSRs(AutoCSR):
     def __init__(self, chan_sel_width,
                  data_width, address_width, full_ts_width):
@@ -300,7 +291,6 @@ class RTIO(Module):
                             for c in channels)
 
         # CSRs
-        self.csrs = _CSRs()
         self.kcsrs = _KernelCSRs(bits_for(len(channels)-1),
                                  data_width, address_width,
                                  counter_width + fine_ts_width)
@@ -405,18 +395,5 @@ class RTIO(Module):
                                                 << fine_ts_width)
            )
 
-        # Frequency CSRs
-        clk_freq = Fraction(clk_freq).limit_denominator(255)
-        clk_freq_i = int(clk_freq)
-        clk_freq_f = clk_freq - clk_freq_i
-        self.comb += [
-            self.csrs.frequency_i.status.eq(clk_freq_i),
-            self.csrs.frequency_fn.status.eq(clk_freq_f.numerator),
-            self.csrs.frequency_fd.status.eq(clk_freq_f.denominator)
-        ]
-
     def get_csrs(self):
-        return self.csrs.get_csrs()
-
-    def get_kernel_csrs(self):
         return self.kcsrs.get_csrs()

benchmarks/ddb.pyon

@@ -9,7 +9,7 @@
         "type": "local",
         "module": "artiq.coredevice.core",
         "class": "Core",
-        "arguments": {}
+        "arguments": {"ref_period": Quantity(Fraction(8, 1000000000), "s")}
     },
 
     "pmt0": {

examples/master/ddb.pyon

@@ -9,7 +9,7 @@
         "type": "local",
         "module": "artiq.coredevice.core",
         "class": "Core",
-        "arguments": {}
+        "arguments": {"ref_period": Quantity(Fraction(8, 1000000000), "s")}
     },
 
     "pmt0": {

soc/runtime/comm_serial.c

@@ -178,16 +178,6 @@ void comm_serve(object_loader load_object, kernel_runner run_kernel)
         if(msgtype == MSGTYPE_REQUEST_IDENT) {
             send_char(MSGTYPE_IDENT);
             send_int(0x41524f52); /* "AROR" - ARTIQ runtime on OpenRISC */
-#ifdef ARTIQ_AMP
-#warning TODO
-            send_int(125*1000*1000);
-            send_char(0);
-            send_char(1);
-#else
-            send_int(rtio_frequency_i_read());
-            send_char(rtio_frequency_fn_read());
-            send_char(rtio_frequency_fd_read());
-#endif
         } else if(msgtype == MSGTYPE_LOAD_OBJECT)
             receive_and_load_object(load_object);
         else if(msgtype == MSGTYPE_RUN_KERNEL)

soc/targets/artiq_kc705.py

@@ -98,7 +98,7 @@ class UP(_Peripherals):
     def __init__(self, *args, **kwargs):
         _Peripherals.__init__(self, *args, **kwargs)
 
-        rtio_csrs = self.rtio.get_csrs() + self.rtio.get_kernel_csrs()
+        rtio_csrs = self.rtio.get_csrs()
         self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
         self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
         self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs)
@@ -127,7 +127,7 @@ class AMP(_Peripherals):
         self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i2)
         self.add_memory_region("mailbox", self.mem_map["mailbox"] + 0x80000000, 4)
 
-        rtio_csrs = self.rtio.get_kernel_csrs()
+        rtio_csrs = self.rtio.get_csrs()
         self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
         self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
         self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs)

soc/targets/artiq_pipistrello.py

@@ -125,7 +125,7 @@ class UP(_Peripherals):
     def __init__(self, platform, **kwargs):
         _Peripherals.__init__(self, platform, **kwargs)
 
-        rtio_csrs = self.rtio.get_csrs() + self.rtio.get_kernel_csrs()
+        rtio_csrs = self.rtio.get_csrs()
         self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
         self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
         self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32,
@@ -158,7 +158,7 @@ class AMP(_Peripherals):
         self.add_memory_region("mailbox",
                                self.mem_map["mailbox"] + 0x80000000, 4)
 
-        rtio_csrs = self.rtio.get_kernel_csrs()
+        rtio_csrs = self.rtio.get_csrs()
         self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
         self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]),
                                      self.rtiowb.bus)

soc/targets/artiq_ppro.py

@@ -112,7 +112,7 @@ class UP(BaseSoC):
                                          clk_freq=125000000,
                                          counter_width=32)
 
-        rtio_csrs = self.rtio.get_csrs() + self.rtio.get_kernel_csrs()
+        rtio_csrs = self.rtio.get_csrs()
         self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
         self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
         self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000,