M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

serwb: transmit zeroes when nothing to transmit (for prbs), improve rx idle detection

This commit is contained in:
Florent Kermarrec 2018-06-08 16:10:31 +02:00
parent 7296a76f18
commit 53e9e475d0
3 changed files with 12 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
artiq/gateware/serwb/datapath.py
View File

@ -185,11 +185,13 @@ class RXDatapath(Module):
]
# idle decoding
idle_timer = WaitTimer(256)
idle_timer = WaitTimer(32)
self.submodules += idle_timer
self.comb += [
idle_timer.wait.eq(1),
idle.eq(idle_timer.done & ((converter.source.data == 0) | (converter.source.data == (2**40-1))))
self.sync += [
If(converter.source.stb,
idle_timer.wait.eq((converter.source.data == 0) | (converter.source.data == (2**40-1)))
),
idle.eq(idle_timer.done)
]
# comma decoding
self.sync += \

2
artiq/gateware/serwb/genphy.py
View File

@ -313,7 +313,9 @@ class SERWBPHY(Module, AutoCSR):
# tx/rx dataflow
self.comb += [
If(self.init.ready,
If(sink.stb,
sink.connect(self.serdes.tx.sink),
),
self.serdes.rx.source.connect(source)
).Else(
self.serdes.rx.source.ack.eq(1)

2
artiq/gateware/serwb/phy.py
View File

@ -362,7 +362,9 @@ class SERWBPHY(Module, AutoCSR):
# tx/rx dataflow
self.comb += [
If(self.init.ready,
If(sink.stb,
sink.connect(self.serdes.tx.sink),
),
self.serdes.rx.source.connect(source)
).Else(
self.serdes.rx.source.ack.eq(1)