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sawg: explain DUC
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@ -91,7 +91,8 @@ class Config:
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@kernel
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@kernel
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def set_duc_i_max(self, limit: TInt32):
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def set_duc_i_max(self, limit: TInt32):
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"""Set the DUC I data summing junction upper limit.
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"""Set the digital up-converter (DUC) I data summing junction upper
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limit.
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Each of the three summing junctions has a saturating adder with
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Each of the three summing junctions has a saturating adder with
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configurable upper and lower limits. The three summing junctions are:
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configurable upper and lower limits. The three summing junctions are:
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@ -169,6 +170,14 @@ class SAWG:
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i_enable*Re(oscillators) +
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i_enable*Re(oscillators) +
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q_enable*Im(buddy_oscillators))
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q_enable*Im(buddy_oscillators))
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This parametrization can be viewed as two complex (quadrature) oscillators
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(``frequency1``/``phase1`` and ``frequency2``/``phase2``) followed by
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a complex digital up-converter (DUC, ``frequency0``/``phase0``) on top of a
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(real/in-phase) ``offset``. The ``i_enable``/``q_enable`` switches
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enable emission of quadrature signals for later analog quadrature mixing
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distinguishing upper and lower sidebands and thus doubling the bandwidth.
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They can also be used to emit four-tone signals.
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The configuration channel and the nine spline interpolators are accessible
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The configuration channel and the nine spline interpolators are accessible
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as attributes:
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as attributes:
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