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firmware/runtime: Fix Ext0_Synth0_*to125 log messages

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David Nadlinger 2022-12-02 01:37:56 +00:00 committed by Sebastien Bourdeauducq
parent 47581e0de9
commit 520692073e
1 changed files with 2 additions and 2 deletions
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4
artiq/firmware/runtime/rtio_clocking.rs
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@ -134,7 +134,7 @@ fn setup_si5324_as_synthesizer(cfg: RtioClock) {
} }
}, },
RtioClock::Ext0_Synth0_100to125 => { // 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth RtioClock::Ext0_Synth0_100to125 => { // 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth
info!("using 10MHz reference to make 125MHz RTIO clock with PLL"); info!("using 100MHz reference to make 125MHz RTIO clock with PLL");
si5324::FrequencySettings { si5324::FrequencySettings {
n1_hs : 10, n1_hs : 10,
nc1_ls : 4, nc1_ls : 4,
@ -147,7 +147,7 @@ fn setup_si5324_as_synthesizer(cfg: RtioClock) {
} }
}, },
RtioClock::Ext0_Synth0_125to125 => { // 125MHz output, from 125MHz CLKINx reference, 606 Hz loop bandwidth RtioClock::Ext0_Synth0_125to125 => { // 125MHz output, from 125MHz CLKINx reference, 606 Hz loop bandwidth
info!("using 10MHz reference to make 125MHz RTIO clock with PLL"); info!("using 125MHz reference to make 125MHz RTIO clock with PLL");
si5324::FrequencySettings { si5324::FrequencySettings {
n1_hs : 5, n1_hs : 5,
nc1_ls : 8, nc1_ls : 8,