M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 1
Code Issues Projects Releases Wiki Activity

wrpll: more careful I2C timing

This commit is contained in:
Sebastien Bourdeauducq 2020-01-14 20:03:46 +08:00
parent 105dd60c78
commit 50302d57c0
1 changed files with 21 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
artiq/gateware/drtio/wrpll/si549.py
View File

@ -49,8 +49,6 @@ class I2CMasterMachine(Module):
self.ready.eq(1), self.ready.eq(1),
If(self.start, If(self.start,
NextState("START0"), NextState("START0"),
).Elif(self.stop & self.start,
NextState("RESTART0"),
).Elif(self.stop, ).Elif(self.stop,
NextState("STOP0"), NextState("STOP0"),
).Elif(self.write, ).Elif(self.write,
@ -62,40 +60,44 @@ class I2CMasterMachine(Module):
fsm.act("START0", fsm.act("START0",
NextValue(self.scl, 1), NextValue(self.scl, 1),
NextState("START1")) NextState("START1")
)
fsm.act("START1", fsm.act("START1",
NextValue(self.sda_o, 0), NextValue(self.sda_o, 0),
NextState("IDLE")) NextState("IDLE")
)
fsm.act("RESTART0",
NextValue(self.scl, 0),
NextState("RESTART1"))
fsm.act("RESTART1",
NextValue(self.sda_o, 1),
NextState("START0"))
fsm.act("STOP0", fsm.act("STOP0",
NextValue(self.scl, 0), NextValue(self.scl, 0),
NextState("STOP1")) NextState("STOP1")
)
fsm.act("STOP1", fsm.act("STOP1",
NextValue(self.scl, 1),
NextValue(self.sda_o, 0), NextValue(self.sda_o, 0),
NextState("STOP2")) NextState("STOP2")
)
fsm.act("STOP2", fsm.act("STOP2",
NextValue(self.scl, 1),
NextState("STOP3")
)
fsm.act("STOP3",
NextValue(self.sda_o, 1), NextValue(self.sda_o, 1),
NextState("IDLE")) NextState("IDLE")
)
fsm.act("WRITE0", fsm.act("WRITE0",
NextValue(self.scl, 0), NextValue(self.scl, 0),
NextState("WRITE1")
)
fsm.act("WRITE1",
If(bits == 0, If(bits == 0,
NextValue(self.sda_o, 1), NextValue(self.sda_o, 1),
NextState("READACK0"), NextState("READACK0"),
).Else( ).Else(
NextValue(self.sda_o, data[7]), NextValue(self.sda_o, data[7]),
NextState("WRITE1"), NextState("WRITE2"),
) )
) )
fsm.act("WRITE1", fsm.act("WRITE2",
NextValue(self.scl, 1), NextValue(self.scl, 1),
NextValue(data[1:], data[:-1]), NextValue(data[1:], data[:-1]),
NextValue(bits, bits - 1), NextValue(bits, bits - 1),
@ -240,6 +242,8 @@ def simulate_programmer():
yield yield
while (yield dut.busy): while (yield dut.busy):
yield yield
for _ in range(20):
yield
run_simulation(dut, generator(), vcd_name="tb.vcd") run_simulation(dut, generator(), vcd_name="tb.vcd")