Phaser: zero oscillator amplitude after `init()` (close #1651)

Currently, `init()` leaves a single oscillator at full scale. The phase
accumulator of this oscillator is held continuously cleared. Provided no
upconverting mechanism is active (DUC, CMIX, NCO), this produces a full-scale
DC voltage. The DC voltage is blocked by hardware capacitors. This behaviour
is not mentioned by the `init` documentation.

If one attempts to use any other oscillator without reducing the amplitude
of the oscillator enabled by `init`, there is by significant clipping.

In the case that the NCO or CMIX are configured via the device_db
(suggested in the docs), leaving the osillator at full scale results in
full RF output power after calling `init()`. This may plausibly damage loads
driven by phaser.

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>

artiq/coredevice/phaser.py

@@ -306,6 +306,9 @@ class Phaser:
             self.duc_stb()
             delay(.1*ms)  # settle link, pipeline and impulse response
             data = channel.get_dac_data()
+            delay(1*us)
+            channel.oscillator[0].set_amplitude_phase_mu(asf=0, pow=0xc000,
+                                                         clr=1)
             delay(.1*ms)
             sqrt2 = 0x5a81  # 0x7fff/sqrt(2)
             data_i = data & 0xffff