From 4f6241283c2504977983c08821ebfe29a06e2620 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 29 Oct 2016 16:37:53 +0800 Subject: [PATCH] drtio: always use NoRetiming on MultiReg inputs --- artiq/gateware/drtio/link_layer.py | 4 +++- artiq/gateware/drtio/rt_controller.py | 7 +++++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/artiq/gateware/drtio/link_layer.py b/artiq/gateware/drtio/link_layer.py index 46626ab77..bf5f771ec 100644 --- a/artiq/gateware/drtio/link_layer.py +++ b/artiq/gateware/drtio/link_layer.py @@ -3,7 +3,7 @@ from operator import xor, or_ from migen import * from migen.genlib.fsm import * -from migen.genlib.cdc import MultiReg +from migen.genlib.cdc import MultiReg, NoRetiming class Scrambler(Module): @@ -248,7 +248,9 @@ class LinkLayer(Module): rx_remote_rx_ready = Signal() rx_link_init = Signal() self.specials += [ + NoRetiming(rx.remote_rx_ready), MultiReg(rx.remote_rx_ready, rx_remote_rx_ready, "rtio"), + NoRetiming(rx.link_init), MultiReg(rx.link_init, rx_link_init, "rtio") ] diff --git a/artiq/gateware/drtio/rt_controller.py b/artiq/gateware/drtio/rt_controller.py index a7ba5f2b6..acee322ee 100644 --- a/artiq/gateware/drtio/rt_controller.py +++ b/artiq/gateware/drtio/rt_controller.py @@ -1,5 +1,5 @@ from migen import * -from migen.genlib.cdc import MultiReg +from migen.genlib.cdc import MultiReg, NoRetiming from misoc.interconnect.csr import * @@ -44,7 +44,10 @@ class RTController(Module): self.sync += If(self.kcsrs.counter_update.re, self.kcsrs.counter.status.eq(self.counter.value_sys)) tsc_correction = Signal(64) - self.specials += MultiReg(self.kcsrs.tsc_correction.storage, tsc_correction) + self.specials += [ + NoRetiming(self.kcsrs.tsc_correction.storage), + MultiReg(self.kcsrs.tsc_correction.storage, tsc_correction) + ] self.comb += [ rt_packets.tsc_value.eq( self.counter.value_rtio + tsc_correction),