diff --git a/soc/targets/artiq_kc705.py b/soc/targets/artiq_kc705.py
index b4b2ae92b..f70eabaab 100644
--- a/soc/targets/artiq_kc705.py
+++ b/soc/targets/artiq_kc705.py
@@ -103,7 +103,7 @@ class ARTIQSoC(BaseSoC):
         rtio_csrs = self.rtio.get_csrs()
         self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
         self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus)
-        self.add_cpu_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
+        self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
 
         dds_pads = platform.request("dds")
         self.submodules.dds = ad9858.AD9858(dds_pads)
diff --git a/soc/targets/artiq_ppro.py b/soc/targets/artiq_ppro.py
index 64c0a370d..23f73bc3d 100644
--- a/soc/targets/artiq_ppro.py
+++ b/soc/targets/artiq_ppro.py
@@ -92,7 +92,8 @@ class ARTIQMiniSoC(BaseSoC):
     }
     csr_map.update(BaseSoC.csr_map)
 
-    def __init__(self, platform, cpu_type="or1k", ramcon_type="minicon",
+    def __init__(self, platform, cpu_type="or1k",
+                 ramcon_type="minicon", with_l2=False,
                  with_test_gen=False, **kwargs):
         BaseSoC.__init__(self, platform,
                          cpu_type=cpu_type, ramcon_type=ramcon_type,
@@ -123,7 +124,7 @@ class ARTIQMiniSoC(BaseSoC):
         rtio_csrs = self.rtio.get_csrs()
         self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
         self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus)
-        self.add_cpu_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
+        self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
 
         if with_test_gen:
             self.submodules.test_gen = _TestGen(platform.request("ttl", 8))