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phaser: spelling

This commit is contained in:
Robert Jördens 2020-09-09 16:52:52 +00:00
parent 8aaeaa604e
commit 4e24700205
1 changed files with 1 additions and 1 deletions
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artiq/gateware/rtio/phy/phaser.py
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@ -12,7 +12,7 @@ class DDSChannel(Module):
enable_replace=True)) enable_replace=True))
to_rio_phy = ClockDomainsRenamer("rio_phy") to_rio_phy = ClockDomainsRenamer("rio_phy")
self.submodules.dds = to_rio_phy(MultiDDS( self.submodules.dds = to_rio_phy(MultiDDS(
n=5, fwidth=32, xwidth=16, z=19, zl=10, shae_lut=share_lut)) n=5, fwidth=32, xwidth=16, z=19, zl=10, share_lut=share_lut))
regs = [] regs = []
for i in self.dds.i: for i in self.dds.i:
regs.extend([i.f, Cat(i.a, i.clr, i.p)]) regs.extend([i.f, Cat(i.a, i.clr, i.p)])