From 4cb9f77fd86cb4ead92592ec0a0602965fa57308 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 13 Jan 2019 13:53:07 +0800 Subject: [PATCH] sayma_amc: fix Master timing constraints --- artiq/gateware/targets/sayma_amc.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index c8f68a5f0..472331944 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -507,16 +507,16 @@ class Master(MiniSoC, AMPSoC): self.add_memory_group("drtioaux_mem", drtioaux_memory_group) rtio_clk_period = 1e9/rtio_clk_freq - gth = self.drtio_transceiver.gths[0] - platform.add_period_constraint(gth.txoutclk, rtio_clk_period/2) - platform.add_period_constraint(gth.rxoutclk, rtio_clk_period) + gth0 = self.drtio_transceiver.gths[0] + platform.add_period_constraint(gth0.txoutclk, rtio_clk_period/2) + platform.add_period_constraint(gth0.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( self.crg.cd_sys.clk, - gth.txoutclk, gth.rxoutclk) + gth0.txoutclk, gth0.rxoutclk) for gth in self.drtio_transceiver.gths[1:]: platform.add_period_constraint(gth.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( - self.crg.cd_sys.clk, gth.rxoutclk) + self.crg.cd_sys.clk, gth0.txoutclk, gth.rxoutclk) self.rtio_channels = rtio_channels = [] for i in range(4):