From 4c27029be0254d803b5e9c520e46e9970869883e Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Tue, 13 Dec 2016 19:20:03 +0100 Subject: [PATCH] sawg: fix limit regs --- artiq/gateware/dsp/sawg.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/dsp/sawg.py b/artiq/gateware/dsp/sawg.py index 080d73fbb..540751be0 100644 --- a/artiq/gateware/dsp/sawg.py +++ b/artiq/gateware/dsp/sawg.py @@ -108,7 +108,7 @@ class Config(Module): Signal((width, True), reset=(1 << width - 1) - 1)] for i in range(3)] self.clipped = [Signal(2) for i in range(3)] # TODO - self.i = Endpoint([("addr", bits_for(4 + len(self.limits))), + self.i = Endpoint([("addr", bits_for(1 + 4 + len(self.limits))), ("data", 16)]) self.ce = Signal() @@ -119,7 +119,7 @@ class Config(Module): pad = Signal() reg = Array([Cat(div, n), self.clr, self.iq_en, pad] + - [Cat(*l) for l in self.limits]) + sum(self.limits, [])) self.comb += [ self.i.ack.eq(1),