From 4b14887ddb0764b19ca22991204a47509ca793db Mon Sep 17 00:00:00 2001 From: whitequark Date: Thu, 16 Mar 2017 03:11:10 +0000 Subject: [PATCH] gateware: work around ISE/Vivado bugs with very wide shifts. --- artiq/gateware/rtio/dma.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/rtio/dma.py b/artiq/gateware/rtio/dma.py index c70bbfa3c..fc12b5b05 100644 --- a/artiq/gateware/rtio/dma.py +++ b/artiq/gateware/rtio/dma.py @@ -14,7 +14,7 @@ class WishboneReader(Module): self.bus = bus aw = len(bus.adr) - dw = len(bus.dat_w) + dw = len(bus.dat_w) self.sink = stream.Endpoint([("address", aw)]) self.source = stream.Endpoint([("data", dw)]) @@ -106,7 +106,9 @@ class RawSlicer(Module): If(load_buf, Case(level, {i: buf[i*g:(i+in_size)*g].eq(self.sink.data) for i in range(out_size)})), - If(shift_buf, buf.eq(buf >> self.source_consume*g)) + If(shift_buf, Case(self.source_consume, + {i: buf.eq(buf[i*g:]) + for i in range(out_size)})), ] fsm = FSM(reset_state="FETCH")