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spi/ad5360: refactor, small fixes
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@ -1,7 +1,8 @@
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from artiq.language.core import kernel, portable, delay
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from artiq.language.units import ns
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from artiq.language.core import kernel, portable, delay_mu
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from artiq.coredevice import spi
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# Designed from the data sheets and somewhat after the linux kernel
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# iio driver.
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_AD5360_SPI_CONFIG = (0*spi.SPI_OFFLINE | 0*spi.SPI_CS_POLARITY |
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0*spi.SPI_CLK_POLARITY | 1*spi.SPI_CLK_PHASE |
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@ -21,7 +22,7 @@ _AD5360_SPECIAL_NOP = 0 << 16
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_AD5360_SPECIAL_CONTROL = 1 << 16
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_AD5360_SPECIAL_OFS0 = 2 << 16
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_AD5360_SPECIAL_OFS1 = 3 << 16
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_AD5360_SPECIAL_READ = 3 << 16
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_AD5360_SPECIAL_READ = 5 << 16
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@portable
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@ -43,11 +44,12 @@ class AD5360:
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multi-channel Digital to Analog Converters
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"""
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def __init__(self, dmgr, spi_bus, ldac=None, chip_select=0):
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def __init__(self, dmgr, spi_device, ldac_device=None,
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chip_select=1):
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self.core = dmgr.get("core")
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self.bus = dmgr.get(spi_bus)
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if ldac is not None:
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ldac = dmgr.get(ldac)
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self.bus = dmgr.get(spi_device)
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if ldac_device is not None:
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ldac = dmgr.get(ldac_device)
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self.ldac = ldac
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self.chip_select = chip_select
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@ -58,32 +60,35 @@ class AD5360:
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self.bus.set_config_mu(_AD5360_SPI_CONFIG, write_div, read_div)
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self.bus.set_xfer(self.chip_select, 24, 0)
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@kernel
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def write(self, data):
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self.bus.write(data << 8)
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delay_mu(self.bus.ref_period_mu) # get to 20ns min cs high
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@kernel
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def write_offsets(self, value=0x1fff):
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value &= 0x3fff
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self.bus.write((_AD5360_CMD_SPECIAL | _AD5360_SPECIAL_OFS0 | value
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) << 8)
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self.bus.write((_AD5360_CMD_SPECIAL | _AD5360_SPECIAL_OFS1 | value
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) << 8)
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self.write(_AD5360_CMD_SPECIAL | _AD5360_SPECIAL_OFS0 | value)
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self.write(_AD5360_CMD_SPECIAL | _AD5360_SPECIAL_OFS1 | value)
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@kernel
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def write_channel(self, channel=0, value=0, op=_AD5360_CMD_DATA):
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channel &= 0x3f
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value &= 0xffff
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self.bus.write((op | _AD5360_WRITE_CHANNEL(channel) | value) << 8)
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self.write(op | _AD5360_WRITE_CHANNEL(channel) | value)
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@kernel
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def write_channels(self, values, first=0, op=_AD5360_CMD_DATA):
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def write_channels(self, values, op=_AD5360_CMD_DATA):
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for i in range(len(values)):
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self.write_channel(i + first, values[i], op)
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self.write_channel(i, values[i], op)
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@kernel
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def read_channel_sync(self, channel=0, op=_AD5360_READ_X1A):
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channel &= 0x3f
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self.bus.write((_AD5360_CMD_SPECIAL | _AD5360_SPECIAL_READ | op |
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_AD5360_READ_CHANNEL(channel)) << 8)
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self.write(_AD5360_CMD_SPECIAL | _AD5360_SPECIAL_READ | op |
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_AD5360_READ_CHANNEL(channel))
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self.bus.set_xfer(self.chip_select, 0, 24)
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self.bus.write((_AD5360_CMD_SPECIAL | _AD5360_SPECIAL_NOP) << 8)
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self.write(_AD5360_CMD_SPECIAL | _AD5360_SPECIAL_NOP)
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self.bus.read_async()
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self.bus.set_xfer(self.chip_select, 24, 0)
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return self.bus.input_async() & 0xffff
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@ -91,5 +96,5 @@ class AD5360:
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@kernel
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def load(self):
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self.ldac.off()
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delay(24*ns)
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delay_mu(3*self.bus.ref_period_mu)
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self.ldac.on()
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@ -38,17 +38,16 @@ class SPIMaster:
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* If desired, :meth:`write` ``data`` queuing the next
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(possibly chained) transfer.
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:param ref_period: clock period of the SPI core.
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:param channel: RTIO channel number of the SPI bus to control.
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"""
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def __init__(self, dmgr, ref_period, channel):
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def __init__(self, dmgr, channel):
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self.core = dmgr.get("core")
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self.ref_period = ref_period
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self.ref_period_mu = int(seconds_to_mu(ref_period, self.core))
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self.ref_period_mu = seconds_to_mu(self.core.coarse_ref_period,
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self.core)
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self.channel = channel
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self.write_period_mu = int(0)
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self.read_period_mu = int(0)
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self.xfer_period_mu = int(0)
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self.write_period_mu = int(0, 64)
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self.read_period_mu = int(0, 64)
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self.xfer_period_mu = int(0, 64)
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# A full transfer takes write_period_mu + xfer_period_mu.
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# Chained transfers can happen every xfer_period_mu.
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# The second transfer of a chain can be written 2*ref_period_mu
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@ -81,7 +81,7 @@
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"arguments": {"channel": 19}
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},
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"ams101_ldac": {
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"ttl_ams101_ldac": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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@ -94,7 +94,7 @@
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"arguments": {"channel": 21}
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},
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"ams101_spi": {
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"spi_ams101": {
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"type": "local",
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"module": "artiq.coredevice.spi",
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"class": "SPIMaster",
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@ -108,6 +108,13 @@
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"arguments": {"channel": 23}
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},
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"dac0": {
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"type": "local",
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"module": "artiq.coredevice.ad5360",
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"class": "AD5360",
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"arguments": {"spi_device": "spi0", "ldac_device": "ttl0"}
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},
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"dds_bus": {
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"type": "local",
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"module": "artiq.coredevice.dds",
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