mirror of https://github.com/m-labs/artiq.git
gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623
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parent
2015fe9de0
commit
4a62e09bd4
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@ -230,16 +230,16 @@ class NIST_CLOCK(_NIST_Ions):
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if i % 4 == 3:
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if i % 4 == 3:
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phy = ttl_serdes_7series.Inout_8X(platform.request("ttl", i))
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phy = ttl_serdes_7series.Inout_8X(platform.request("ttl", i))
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self.submodules += phy
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=1024))
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else:
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else:
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phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
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phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
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self.submodules += phy
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=1024))
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for i in range(2):
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for i in range(2):
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phy = ttl_serdes_7series.Inout_8X(platform.request("pmt", i))
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phy = ttl_serdes_7series.Inout_8X(platform.request("pmt", i))
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self.submodules += phy
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=16384))
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phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n_33"))
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phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n_33"))
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self.submodules += phy
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self.submodules += phy
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@ -279,7 +279,7 @@ class NIST_CLOCK(_NIST_Ions):
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phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
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phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
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self.submodules += phy
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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rtio_channels.append(rtio.Channel.from_phy(phy,
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ofifo_depth=512,
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ofifo_depth=16384,
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ififo_depth=4))
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ififo_depth=4))
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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